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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Total-dose radiation effects data for semiconductor devices. 1985 Supplement. Volume 2, part B

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 (Parts A and B) provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done steady-state 2.5-MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose. All data were generated in support of NASA space programs by the JPL Radiation Effects and Testing Group (514).

Martin, K. E.↗
NASA NTRS1991

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Eldin, A. G.↗
NASA NTRS2015

Complex Parts, Complex Data: Why You Need to Understand What Radiation Single Event Testing Data Does and Doesn't Show and the Implications Thereof

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks from single particle event testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means. Its all about understanding actual risks and not making assumptions.

NASA Electronic Parts and Packaging (NEPP) Program↗
NASA NTRS2006

Submicrosecond Power-Switching Test Circuit

A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a repetitive waveform from a signal generator, momentary closure of a push-button switch, or closure or opening of a manually operated on/off switch. In the case of a signal generator, one can adjust the frequency and duty cycle as needed to obtain the desired AC power-supply response, which one could display on an oscilloscope. Momentary switch closure could be useful for obtaining (and, if desired, displaying on an oscilloscope set to trigger on an event) the response of a power supply to a single load transient. The on/off switch can be used to switch between load states in which static-load regulation measurements are performed.

Folk, Eric N.↗
NASA NTRS1997

Computational Investigation of Experimental Interaction Impedance Obtained by Perturbation for Helical Traveling-Wave Tube Structures

Conventional methods used to measure the cold-test interaction impedance of helical slow-wave structures involve perturbing a helical circuit with a cylindrical dielectric rod placed on the central axis of the circuit. It has been shown that the difference in resonant frequency or axial phase shift between the perturbed and unperturbed circuits can be related to the interaction impedance. However, because of the complex configuration of the helical circuit, deriving this relationship involves-several approximations. With the advent of accurate three- dimensional helical circuit models, these standard approximations can be fully investigated. This paper addresses the most prominent approximations made in the analysis for measured interaction impedance by Lagerstrom and investigates their accuracy using the three-dimensional simulation code MAFIA. It is shown that a more accurate value of interaction impedance can be obtained by using three-dimensional computational methods rather than performing costly and time consuming experimental cold-test measurements.

Kory, Carol L.↗
NASA NTRS1998

Computational Investigation of Experimental Interaction Impedance Obtained by Perturbation for Helical Traveling Wave Tube Structures

Conventional methods used to measure the cold- test interaction impedance of helical slow-wave structures involve perturbing a helical circuit with a cylindrical dielectric rod placed on the central axis of the circuit It has been shown that the difference in resonant frequency or axial phase shift between the perturbed and unperturbed circuits can be related to the interaction impedance. However, because of the complex configuration of the helical circuit, deriving this relationship involves several approximations. With the advent of accurate three-dimensional (3-D) helical circuit models, these standard approximations can be fully Investigated. This paper addresses the most prominent approximations made in the analysis for measured interaction impedance by Lagerstrom and investigates their accuracy using the 3-D simulation code MAFIA. It is shown that a more accurate value of interaction impedance can be obtained by using 3-D computational methods rather than performing costly and time consuming experimental cold-test measurements.

Kory, Carol L.↗
NASA NTRS1998

Computational Investigation of Experimental Interaction Impedance Obtained by Perturbation for Helical Traveling-Wave Tube Structures

Conventional methods used to measure the cold-test interaction impedance of helical slow-wave structures involve perturbing a helical circuit with a cylindrical dielectric rod placed on the central axis of the circuit. It has been shown that the difference in resonant frequency or axial phase shift between the perturbed and unperturbed circuits can be related to the interaction impedance. However, because of the complex configuration of the helical circuit, deriving this relationship involves several approximations. With the advent of accurate three-dimensional (3-D) helical circuit models, these standard approximations can be fully investigated. This paper addresses the most prominent approximations made in the analysis for measured interaction impedance by Lagerstrom and investigates their accuracy using the 3-D simulation code MAFIA. It is shown that a more accurate value of interaction impedance can be obtained by using 3-D computational methods rather than performing costly and time consuming experimental cold-test measurements.

Kory, Carol L.↗
NASA NTRS1990

VLSI Architecture For Viterbi Decoder

"Pipeline" architecture developed for very-large-scale integrated (VLSI) Viterbi decoding circuits for binary convolutional codes of large constraint lengths. In scheme, single sequential processor computes path metrics in trellis diagram (diagram in which paths and nodes represent possible sequences of code states and in which metrics indicate relative likelihoods of sequences). Systolic-array method used to store path information as well as to choose path with best metric. VLSI Viterbi-decoder architecture is compromise between speed and complexity. Size of decoding circuit increases approximately linearly with constraint length of code, and additional circuit chips added with moderate numbers of interconnections.

Hsu, In-Shek↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS1974

The problem of controlling the directivity of low directivity antennas on spacecraft in flight

Interests exist in the creation of antennas allowing adjustment of the radiation pattern and directivity in flight without using complex switching and matching circuits. Results are presented of certain experimental tests performed with log-periodic conical helical antennas to determine the possibilities of regulation of their radiation patterns without changing the structure of the current-carrying elements, supply connections, etc.

Mashkov, V. I.↗
NASA NTRS1977

Direct-reading inductance meter

Meter indicates from 30 nH to 3 micro H. Reference inductor of 15 micro H is made by winding 50 turns of Number 26 Formvar wire on Micrometal type 50-2 (or equivalent) core. Circuit eliminates requirement for complex instrument compensation prior to taking coil inductance measurement and thus is as easy to operate as common ohmmeter.

Kolbly, R. B.↗
NASA NTRS1992

A fixed tuned broadband matching structure for submillimeter SIS receivers

We have designed, fabricated, and tested a quasi-optical spiral antenna mixer with a Nb/AlO(x)/Nb tunnel junction. This design incorporates a hybrid antenna fed by a planar logarithmic spiral antenna to couple to the radiation field, as previously done with Pb based devices, as well as a newly designed matching circuit. This matching circuit is a relatively complex structure requiring several layers of photolithographic processing on top of the actual tunneling device. Computer modeling of the device predicted the measured bandwidth to within 8 percent, making scale model measurements unnecessary. We have obtained a good match from 210 GHz to 460 GHz between the antenna and a relatively large area (1.25 by 1.25 sq microns) tunnel junction with omega R(sub N) C approx. = 2 - 4.4. This compares to simple inductive stubs that attain only a few percent of total bandwidth in the submillimeter band or inductively tuned SIS arrays with an upper limit of operating frequencies well below the submillimeter band. Noise temperatures were measured at 345 GHz, 426 GHz, and 492 GHz yielding double sideband noise temperatures at 200 K, 220 K, and 500 K, respectively.

Buettgenbach, Thomas H.↗
NASA NTRS1995

Full-Wave Analysis Of MMICs Using A Generalized Yee Algorithm

Improved method of temporal analysis of propagation of electro-magnetic waves in monolithic microwave integrated circuits (MMICs) implemented by generalized version of traditional Yee algorithm. Provides more accurate mathematical modeling for analysis and design of MMICs. Based on unstructured and otherwise irregular grids. Grids readily fitted to conductive and dielectric circuit elements having realistically complex three-dimensional shapes. Better for modeling important and geometrically complex phenomena like fringing fields.

Lansing, Faiza S.↗
NASA NTRS2001

Novel Multiplexing Technique for Detector and Mixer Arrays

Future submillimeter and far-infrared space telescopes will require large-format (many 1000's of elements) imaging detector arrays to perform state-of-the-art astronomical observations. A crucial issue related to a focal plane array is a readout scheme which is compatible with large numbers of cryogenically-cooled (typically < 1 K) detectors elements. When the number of elements becomes of the order of thousands, the physical layout for individual readout amplifiers becomes nearly impossible to realize for practical systems. Another important concern is the large number of wires leading to a 0.1-0.3 K platform. In the case of superconducting transition edge sensors (TES), a scheme for time-division multiplexing of SQUID read-out amplifiers has been recently demonstrated. In this scheme the number of SQUIDs is equal to the number (N) of the detectors, but only one SQUID is turned on at a time. The SQUIDs are connected in series in each column of the array, so the number of wires leading to the amplifiers can be reduced, but it is still of the order of N. Another approach uses a frequency domain multiplexing scheme of the bolometer array. The bolometers are biased with ac currents whose frequencies are individual for each element and are much higher than the bolometer bandwidth. The output signals are connected in series in a summing loop which is coupled to a single SQUID amplifier. The total number of channels depends on the ratio between the SQUID bandwidth and the bolometer bandwidth and can be at least 100 according to the authors. An important concern about this technique is a contribution of the out-of-band Johnson noise which multiplies by factor N(exp 1/2) for each frequency channel. We propose a novel solution for large format arrays based on the Hadamard transform coding technique which requires only one amplifier to read out the entire array of potentially many 1000's of elements and uses approximately 10 wires between the cold stage and room temperature electronics. This can significantly reduce the complexity of the readout circuits.

Karasik, Boris S.↗
NASA NTRS2001

Experiments on the evolution of digital to analog converters

Currently, there is a research effort in Evolvable Hardware being driven towards two purposes: the synthesis of circuits of medium to high complexity; and the design of reconfigurable architectures that facilitate the system evolvability and on-chip implementation of the evolved circuits. This work addresses these issues by describing the evolution of Digital to Analog Converters (DACs).

DACs evolvable hardware hierarchical evolution gen↗
NASA NTRS2007

Electromagnetic Radial Forces in a Hybrid Eight-Stator-Pole, Six-Rotor-Pole Bearingless Switched-Reluctance Motor

Analysis and experimental measurement of the electromagnet force loads on the hybrid rotor in a novel bearingless switched-reluctance motor (BSRM) have been performed. A BSRM has the combined characteristics of a switched-reluctance motor and a magnetic bearing. The BSRM has an eight-pole stator and a six-pole hybrid rotor, which is composed of circular and scalloped lamination segments. The hybrid rotor is levitated using only one set of stator poles. A second set of stator poles imparts torque to the scalloped portion of the rotor, which is driven in a traditional switched reluctance manner by a processor. Analysis was done for nonrotating rotor poles that were oriented to achieve maximum and minimum radial force loads on the rotor. The objective is to assess whether simple one-dimensional magnetic circuit analysis is sufficient for preliminary evaluation of this machine, which may exhibit strong three-dimensional electromagnetic field behavior. Two magnetic circuit geometries, approximating the complex topology of the magnetic fields in and around the hybrid rotor, were employed in formulating the electromagnetic radial force equations. Reasonable agreement between the experimental results and the theoretical predictions was obtained with typical magnetic bearing derating factors applied to the predictions.

Morrison, Carlos R.↗
NASA NTRS2008

Electromagnetic Forces in a Hybrid Magnetic-Bearing Switched-Reluctance Motor

Analysis and experimental measurement of the electromagnetic force loads on the hybrid rotor in a novel hybrid magnetic-bearing switched-reluctance motor (MBSRM) have been performed. A MBSRM has the combined characteristics of a switched-reluctance motor and a magnetic bearing. The MBSRM discussed in this report has an eight-pole stator and a six-pole hybrid rotor, which is composed of circular and scalloped lamination segments. The hybrid rotor is levitated using only one set of four stator poles, while a second set of four stator poles imparts torque to the scalloped portion of the rotor, which is driven in a traditional switched reluctance manner by a processor. Static torque and radial force analysis were done for rotor poles that were oriented to achieve maximum and minimum radial force loads on the rotor. The objective is to assess whether simple one-dimensional magnetic circuit analysis is sufficient for preliminary evaluation of this machine, which may exhibit strong three-dimensional electromagnetic field behavior. Two magnetic circuit geometries, approximating the complex topology of the magnetic fields in and around the hybrid rotor, were employed in formulating the electromagnetic radial force equations. Reasonable agreement between the experimental and the theoretical radial force loads predictions was obtained with typical magnetic bearing derating factors applied to the predictions.

Morrison, Carlos R.↗
NASA NTRS2010

Static Characteristics of the Ferroelectric Transistor Inverter

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Mitchell, Cody↗