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All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Performance analysis of a cascaded coding scheme with interleaved outer code

A cascaded coding scheme for a random error channel with a bit-error rate is analyzed. In this scheme, the inner code C sub 1 is an (n sub 1, m sub 1l) binary linear block code which is designed for simultaneous error correction and detection. The outer code C sub 2 is a linear block code with symbols from the Galois field GF (2 sup l) which is designed for correcting both symbol errors and erasures, and is interleaved with a degree m sub 1. A procedure for computing the probability of a correct decoding is presented and an upper bound on the probability of a decoding error is derived. The bound provides much better results than the previous bound for a cascaded coding scheme with an interleaved outer code. Example schemes with inner codes ranging from high rates to very low rates are evaluated. Several schemes provide extremely high reliability even for very high bit-error rates say 10 to the -1 to 10 to the -2 power.

Lin, S.↗
NASA NTRS1986

A cascaded coding scheme for error control and its performance analysis

A coding scheme is investigated for error control in data communication systems. The scheme is obtained by cascading two error correcting codes, called the inner and outer codes. The error performance of the scheme is analyzed for a binary symmetric channel with bit error rate epsilon <1/2. It is shown that if the inner and outer codes are chosen properly, extremely high reliability can be attained even for a high channel bit error rate. Various specific example schemes with inner codes ranging form high rates to very low rates and Reed-Solomon codes as inner codes are considered, and their error probabilities are evaluated. They all provide extremely high reliability even for very high bit error rates. Several example schemes are being considered by NASA for satellite and spacecraft down link error control.

Lin, Shu↗
NASA NTRS1994

Error coding simulations in C

When data is transmitted through a noisy channel, errors are produced within the data rendering it indecipherable. Through the use of error control coding techniques, the bit error rate can be reduced to any desired level without sacrificing the transmission data rate. The Astrionics Laboratory at Marshall Space Flight Center has decided to use a modular, end-to-end telemetry data simulator to simulate the transmission of data from flight to ground and various methods of error control. The simulator includes modules for random data generation, data compression, Consultative Committee for Space Data Systems (CCSDS) transfer frame formation, error correction/detection, error generation and error statistics. The simulator utilizes a concatenated coding scheme which includes CCSDS standard (255,223) Reed-Solomon (RS) code over GF(2(exp 8)) with interleave depth of 5 as the outermost code, (7, 1/2) convolutional code as an inner code and CCSDS recommended (n, n-16) cyclic redundancy check (CRC) code as the innermost code, where n is the number of information bits plus 16 parity bits. The received signal-to-noise for a desired bit error rate is greatly reduced through the use of forward error correction techniques. Even greater coding gain is provided through the use of a concatenated coding scheme. Interleaving/deinterleaving is necessary to randomize burst errors which may appear at the input of the RS decoder. The burst correction capability length is increased in proportion to the interleave depth. The modular nature of the simulator allows for inclusion or exclusion of modules as needed. This paper describes the development and operation of the simulator, the verification of a C-language Reed-Solomon code, and the possibility of using Comdisco SPW(tm) as a tool for determining optimal error control schemes.

Noble, Viveca K.↗
NASA NTRS1986

A cascaded coding scheme for error control and its performance analysis

A coding scheme for error control in data communication systems is investigated. The scheme is obtained by cascading two error correcting codes, called the inner and the outer codes. The error performance of the scheme is analyzed for a binary symmetric channel with bit error rate epsilon < 1/2. It is shown that, if the inner and outer codes are chosen properly, extremely high reliability can be attained even for a high channel bit error rate. Various specific example schemes with inner codes ranging from high rates to very low rates and Reed-Solomon codes are considered, and their probabilities are evaluated. They all provide extremely high reliability even for very high bit error rates, say 0.1 to 0.01. Several example schemes are being considered by NASA for satellite and spacecraft down link error control.

Lin, S.↗
NASA NTRS1982

The effects of transmitter/receiver clock time-base instability on coherent communication system performance

The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit-error probability. The types of time-base instability modeled and analyzed include what is commonly referred to as bit jitter (epoch jitter), bit-jitter rate (time interval jitter), and data asymmetry. The bit-error probability is determined as a function of the statistical characteristics of the time-base instability, the data-transition density, the signal-to-noise ratio in the bit-rate bandwidth and the mechanizations of both the data-bit detector and bit synchronizer. The latter is manifested through the bit synchronizer's natural frequency and loop-damping parameters. Numerical results which indicate the sensitivity of the system bit-error rate to various parameters of the model are provided.

Chie, C. M.↗
NASA NTRS2002

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

flash memory program disturb wearout erase fail re↗
NASA NTRS1998

Pulse Shaped 8-PSK Bandwidth Efficiency and Spectral Spike Elimination

The most bandwidth-efficient communication methods are imperative to cope with the congested frequency bands. Pulse shaping methods have excellent effects on narrowing bandwidth and increasing band utilization. The position of the baseband filters for the pulse shaping is crucial. Post-modulation pulse shaping (a low pass filter is located after the modulator) can change signals from constant envelope to non-constant envelope, and non-constant envelope signals through non-linear device (a SSPA or TWT) can further spread the power spectra. Pre-modulation pulse shaping (a filter is located before the modulator) will have constant envelope. These two pulse shaping methods have different effects on narrowing the bandwidth and producing bit errors. This report studied the effect of various pre-modulation pulse shaping filters with respect to bandwidth, spectral spikes and bit error rate. A pre-modulation pulse shaped 8-ary Phase Shift Keying (8PSK) modulation was used throughout the simulations. In addition to traditional pulse shaping filters, such as Bessel, Butterworth and Square Root Raised Cosine (SRRC), other kinds of filters or pulse waveforms were also studied in the pre-modulation pulse shaping method. Simulations were conducted by using the Signal Processing Worksystem (SPW) software package on HP workstations which simulated the power spectral density of pulse shaped 8-PSK signals, end to end system performance and bit error rates (BERS) as a function of Eb/No using pulse shaping in an AWGN channel. These results are compared with the post-modulation pulse shaped 8-PSK results. The simulations indicate traditional pulse shaping filters used in pre-modulation pulse shaping may produce narrower bandwidth, but with worse BER than those in post-modulation pulse shaping. Theory and simulations show pre- modulation pulse shaping could also produce discrete line power spectra (spikes) at regular frequency intervals. These spikes may cause interference with adjacent channel and reduce power efficiency. Some particular pulses (filters), such as trapezoid and pulses with different transits (such as weighted raised cosine transit) were found to reduce bandwidth and not generate spectral spikes. Although a solid state power amplifier (SSPA) was simulated in the non-linear (saturation) region, output power spectra did not spread due to the constant envelope 8-PSK signals.

Tao, Jian-Ping↗
NASA NTRS2005

Packet-Based Protocol Efficiency for Aeronautical and Satellite Communications

This paper examines the relation between bit error ratios and the effective link efficiency when transporting data with a packet-based protocol. Relations are developed to quantify the impact of a protocol s packet size and header size relative to the bit error ratio of the underlying link. These relations are examined in the context of radio transmissions that exhibit variable error conditions, such as those used in satellite, aeronautical, and other wireless networks. A comparison of two packet sizing methodologies is presented. From these relations, the true ability of a link to deliver user data, or information, is determined. Relations are developed to calculate the optimal protocol packet size forgiven link error characteristics. These relations could be useful in future research for developing an adaptive protocol layer. They can also be used for sizing protocols in the design of static links, where bit error ratios have small variability.

Carek, David A.↗
NASA NTRSDate not supplied

NOR Flash Memory Scrubbing Application for Boot File Preservation of NASA’s Descent and Landing Computer (DLC)

Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE) project continues, specifically with this development of the Descent and Landing Computer (DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementation of algorithms and operation of sensors to autonomously guide a spacecraft in performing more precise and safer landings on celestial bodies such as the Moon and Mars [1]. The second iteration of the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalities is the ability to preserve the fidelity of the system’s boot file through the use of memory scrubbing [2]. The ETU has two primary boards, one for housing a Multi-Processor System on a Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA*. To emulate a memory scrubbing function implemented on the ETU’s FPGA board, the design and testing of a software application was performed on a Xilinx KCU105 FPGA evaluation board. The memory scrubbing application had to meet certain key criteria such as (1) properly utilize with the flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memory properly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able to correct all detected errors, and (4) perform memory scrubbing indefinitely and autonomously. A prototype implementation was constructed and tested, demonstrating successful detection and correction of bit errors in multiple configurations. In the form of burst errors or singular bit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the application was successful in preserving memory fidelity.

Flash memory↗
NASA NTRS1984

Performance of OOK and low-order PPM modulations in optical communications when using APD-based receivers

The paper computes direct detection laser communications receiver performance when using avalanche photodiode (APD) detectors. The performances are compared in terms of bit error probability vs average signal required per bit when the transmitter uses either on-off keying (OOK) or low-order PPM formats. It is shown that QPPM requires 3 dB less signal than OOK, while BPPM requires the same or slightly more than OOK for the same performance. Optimum APD gain values range from 200 to 400. When using QPPM, k(eff) = 0.006, and optimum gain, 60 signal counts/bit are required at 500 Mbits/s for a 0.000001 bit error probability. It is concluded that QPPM may be an attractive signaling format for some fiber or free space laser communication applications.

Abshire, J. B.↗
NASA NTRS1999

Punctured Parallel and Serial Concatenated Convolutional Codes for BPSK/QPSK Channels

As available bandwidth for communication applications becomes scarce, bandwidth-efficient modulation and coding schemes become ever important. Since their discovery in 1993, turbo codes (parallel concatenated convolutional codes) have been the center of the attention in the coding community because of their bit error rate performance near the Shannon limit. Serial concatenated convolutional codes have also been shown to be as powerful as turbo codes. In this dissertation, we introduce algorithms for designing bandwidth-efficient rate r = k/(k + 1),k = 2, 3,..., 16, parallel and rate 3/4, 7/8, and 15/16 serial concatenated convolutional codes via puncturing for BPSK/QPSK (Binary Phase Shift Keying/Quadrature Phase Shift Keying) channels. Both parallel and serial concatenated convolutional codes have initially, steep bit error rate versus signal-to-noise ratio slope (called the -"cliff region"). However, this steep slope changes to a moderate slope with increasing signal-to-noise ratio, where the slope is characterized by the weight spectrum of the code. The region after the cliff region is called the "error rate floor" which dominates the behavior of these codes in moderate to high signal-to-noise ratios. Our goal is to design high rate parallel and serial concatenated convolutional codes while minimizing the error rate floor effect. The design algorithm includes an interleaver enhancement procedure and finds the polynomial sets (only for parallel concatenated convolutional codes) and the puncturing schemes that achieve the lowest bit error rate performance around the floor for the code rates of interest.

Acikel, Omer Fatih↗
NASA NTRS1988

Performance of the ICAO standard core service modulation and coding techniques

Aviation binary phase shift keying (A-BPSK) is described and simulated performance results are given that demonstrate robust performance in the presence of hardlimiting amplifiers. The performance of coherently-detected A-BPSK with rate 1/2 convolutional coding are given. The performance loss due to the Rician fading was shown to be less than 1 dB over the simulated range. A partially coherent detection scheme that does not require carrier phase recovery was described. This scheme exhibits similiar performance to coherent detection, at high bit error rates, while it is superior at lower bit error rates.

Lodge, John↗
NASA NTRS2004

Traveling Wave Tube (TVT) RF Power Combining Demonstration for use in the Jupiter Icy Moons Orbiter (JIMO)

The Jupiter Icy Moons Orbiter (JIMO) is set to launch between the years 2012 and 2015. It will possibly utilize a nuclear reactor power source and ion engines as it travels to the moons of Jupiter. The nuclear reactor will produce hundreds of kilowatts of power for propulsion, communication and various scientific instruments. Hence, the RF amplification devices aboard will be able to operate at a higher power level and data rate. The initial plan for the communications system is for an output of 1000 watts of RF power, a data rate of at least 10 megabits a second, and a frequency of 32 GHz. A higher data rate would be ideal to fully utilize the instruments aboard JIMO. At NASA Glenn, one of our roles in the JIMO project is to demonstrate RF power combining using multiple traveling wave tubes (TWT). In order for the power of separate TWT s to be combined, the RF output waves from each must be in-phase and have the same amplitude. Since different tubes act differently, we had to characterize each tube using a Network Analyzer. We took frequency sweeps and power sweeps to characterize each tube to ensure that they will behave similarly under the same conditions. The 200 watt Dornier tubes had been optimized to run at a lower power level (120 watts) for their extensive use in the ACTS program, so we also had to experiment with adjusting the voltage settings on several internal components (helix, anode, collector) of the tubes to reach the full 200 watt potential. from the ACTS program. Phase shifters and power attenuators were placed in the waveguide circuit at the inputs to the tubes so that adjustments could be made individually to match them exactly. A magic tee was used to route and combine the amplified electromagnetic RF waves on the tube output side. The demonstration of 200 watts of combined power was successful with efficiencies greater than 90% over a 500 MHz bandwidth. The next step will be to demonstrate the use of three amplifiers using two magic tees by adding a 200 watt Dornier tube to the Varian and Logimetrics combined setup for a total of 400 watts. After that we will use two 200 watt Dorniers for 400 watts and eventually four 200 watt Dornier tubes to demonstrate 800 watts. After demonstrating the success of power combining, we will need to verify the integrity of a modulated signal sent through the combined tubes. The purpose will be to see what effects separating and recombining will have on the modulated signal and also what effect it will have on combining efficiency. A Bit Error Rate (BER) will be determined by a Bit Error Rate Tester (BERT) by comparing the random information it transmits to what it receives back. The process began with two 100 watt tubes, a Varian and a Logimetrics, salvaged

Downey, Joseph A.↗
NASA NTRS1990

Masking of errors in transmission of VAPC-coded speech

A subjective evaluation is provided of the bit error sensitivity of the message elements of a Vector Adaptive Predictive (VAPC) speech coder, along with an indication of the amenability of these elements to a popular error masking strategy (cross frame hold over). As expected, a wide range of bit error sensitivity was observed. The most sensitive message components were the short term spectral information and the most significant bits of the pitch and gain indices. The cross frame hold over strategy was found to be useful for pitch and gain information, but it was not beneficial for the spectral information unless severe corruption had occurred.

Cox, Neil B.↗
NASA NTRS1972

Design of communication systems using short-constraint-length convolutional codes.

A method is presented for calculating the effect of carrier-phase reference error in a receiver phase-locked loop on bit error rates in convolutionally coded data, for the practical design of systems using short-constraint-length convolutional codes. A set of design curves shows the relation between design bit error rate, uplink carrier tracking loop SNR, downlink total SNR, and downlink modulation index. These curves make possible rapid and simple system optimization.

Merrill, H. M.↗
NASA NTRS1998

Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes

A code trellis is a graphical representation of a code, block or convolutional, in which every path represents a codeword (or a code sequence for a convolutional code). This representation makes it possible to implement Maximum Likelihood Decoding (MLD) of a code with reduced decoding complexity. The most well known trellis-based MLD algorithm is the Viterbi algorithm. The trellis representation was first introduced and used for convolutional codes [23]. This representation, together with the Viterbi decoding algorithm, has resulted in a wide range of applications of convolutional codes for error control in digital communications over the last two decades. There are two major reasons for this inactive period of research in this area. First, most coding theorists at that time believed that block codes did not have simple trellis structure like convolutional codes and maximum likelihood decoding of linear block codes using the Viterbi algorithm was practically impossible, except for very short block codes. Second, since almost all of the linear block codes are constructed algebraically or based on finite geometries, it was the belief of many coding theorists that algebraic decoding was the only way to decode these codes. These two reasons seriously hindered the development of efficient soft-decision decoding methods for linear block codes and their applications to error control in digital communications. This led to a general belief that block codes are inferior to convolutional codes and hence, that they were not useful. Chapter 2 gives a brief review of linear block codes. The goal is to provide the essential background material for the development of trellis structure and trellis-based decoding algorithms for linear block codes in the later chapters. Chapters 3 through 6 present the fundamental concepts, finite-state machine model, state space formulation, basic structural properties, state labeling, construction procedures, complexity, minimality, and sectionalization of trellises. Chapter 7 discusses trellis decomposition and subtrellises for low-weight codewords. Chapter 8 first presents well known methods for constructing long powerful codes from short component codes or component codes of smaller dimensions, and then provides methods for constructing their trellises which include Shannon and Cartesian product techniques. Chapter 9 deals with convolutional codes, puncturing, zero-tail termination and tail-biting.Chapters 10 through 13 present various trellis-based decoding algorithms, old and new. Chapter 10 first discusses the application of the well known Viterbi decoding algorithm to linear block codes, optimum sectionalization of a code trellis to minimize computation complexity, and design issues for IC (integrated circuit) implementation of a Viterbi decoder. Then it presents a new decoding algorithm for convolutional codes, named Differential Trellis Decoding (DTD) algorithm. Chapter 12 presents a suboptimum reliability-based iterative decoding algorithm with a low-weight trellis search for the most likely codeword. This decoding algorithm provides a good trade-off between error performance and decoding complexity. All the decoding algorithms presented in Chapters 10 through 12 are devised to minimize word error probability. Chapter 13 presents decoding algorithms that minimize bit error probability and provide the corresponding soft (reliability) information at the output of the decoder. Decoding algorithms presented are the MAP (maximum a posteriori probability) decoding algorithm and the Soft-Output Viterbi Algorithm (SOVA) algorithm. Finally, the minimization of bit error probability in trellis-based MLD is discussed.

Lin, Shu↗
NASA NTRS1993

Error coding simulations

There are various elements such as radio frequency interference (RFI) which may induce errors in data being transmitted via a satellite communication link. When a transmission is affected by interference or other error-causing elements, the transmitted data becomes indecipherable. It becomes necessary to implement techniques to recover from these disturbances. The objective of this research is to develop software which simulates error control circuits and evaluate the performance of these modules in various bit error rate environments. The results of the evaluation provide the engineer with information which helps determine the optimal error control scheme. The Consultative Committee for Space Data Systems (CCSDS) recommends the use of Reed-Solomon (RS) and convolutional encoders and Viterbi and RS decoders for error correction. The use of forward error correction techniques greatly reduces the received signal to noise needed for a certain desired bit error rate. The use of concatenated coding, e.g. inner convolutional code and outer RS code, provides even greater coding gain. The 16-bit cyclic redundancy check (CRC) code is recommended by CCSDS for error detection.

Noble, Viveca K.↗