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At least 91 records · Page 5

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NASA NTRS1988

On the viscoplastic response of a composite wafer

In the present treatment of a viscoplastic composite wafer formed from a viscoplastic matrix that is reinforced by elastic or viscoplastic fibers attached to its plane surfaces, one constitutive equation is established by considering the viscoplastic behavior of the matrix as determined by an integral-type constitutive law whose intrinsic time-measure is pertinent to endochronic viscoplasticity. Attention is given to asymptotic cases where fiber stiffnesses and the hydrostatic modulus of the wafer are much larger than the latter's shear modulus. An explicit calculation is used when the stress field is uniaxial.

Valanis, K. C.↗

NASA NTRS1990

Growth of high quality 6H-SiC epitaxial films on vicinal (0001) 6H-SiC wafers

Previously reported growth of SiC films on SiC by chemical vapor deposition (CVD) used alpha-SiC crystal substrates. The CVD growth and evaluation of high quality 6H-SiC films on 6H-SiC wafers cut from large boules grown by the modified-sublimation process is reported. The single-crystal 6H-SiC films were grown on wafers oriented 3 to 4 deg off the (0001) plane toward the 11-20 direction. The films, up to 12 microns thick, had surfaces that were smooth and featureless. The high quality of the films was demonstrated by optical and electron microscopy, and low-temperature photoluminescence.

Powell, J. A.↗

NASA NTRS1991

Thermal and structural assessments of a ceramic wafer seal in hypersonic engines

The thermal and structural performances of a ceramic wafer seal in a simulated hypersonic engine environment are numerically assessed. The effects of aerodynamic heating, surface contact conductance between the seal and its adjacent surfaces, flow of purge coolant gases, and leakage of hot engine flow path gases on the seal temperature were investigated from the engine inlet back to the entrance region of the combustion chamber. Finite element structural analyses, coupled with Weibull failure analyses, were performed to determine the structural reliability of the wafer seal.

Tong, Mike T.↗

NASA NTRS1991

Thermal and structural assessments of a ceramic wafer seal in hypersonic engine

Tong, Mike↗

NASA NTRS1992

Evaluation of an innovative high temperature ceramic wafer seal for hypersonic engine applications

A critical mechanical system in advanced hypersonic engines is the panel-edge seal system that seals gaps between the articulating engine panels and the adjacent engine splitter walls. Significant advancements in seal technology are required to meet the extreme demands placed on the seals, including the simultaneous requirements of low leakage, conformable, high temperature, high pressure, sliding operation. In this investigation, the design, development, analytical and experimental evaluation of a new ceramic wafer seal that shows promise of meeting these demands will be addressed. A high temperature seal test fixture was designed and fabricated to measure static seal leakage performance under engine simulated conditions. Ceramic wafer seal leakage rates are presented for engine-simulated air pressure differentials (up to 100 psi), and temperature (up to 1350 F), sealing both flat and distorted wall conditions, where distortions can be as large as 0.15 inches in only an 18 inch span. Seal leakage rates are low, meeting an industry-established tentative leakage limit for all combinations of temperature, pressure and wall conditions considered. A seal leakage model developed from externally-pressurized gas film bearing theory is also presented. Predicted leakage rates agree favorably with the measured data for nearly all conditions of temperature and pressure. Discrepancies noted at high engine pressure and temperature are attributed to thermally-induced, non-uniform changes in the size and shape of the leakage gap condition. The challenging thermal environment the seal must operate in places considerable demands on the seal concept and material selection. Of the many high temperature materials considered in the design, ceramics were the only materials that met the many challenging seal material design requirements. Of the aluminum oxide, silicon carbide, and silicon nitride ceramics considered in the material ranking scheme developed herein, the silicon nitride class of ceramics ranked the highest because of their high temperature strength; resistance to the intense heating rates; resistance to hydrogen damage; and good structural properties. Baseline seal feasibility has been established through the research conducted in this investigation. Recommendations for future work are also discussed.

Steinetz, Bruce M.↗

NASA NTRS1992

Growth and characterizaton of 3C-SiC and 6H-SiC films on 6H-SiC wafers

Single crystal SiC films were grown by CVD on vicinal (0001) SiC wafers cut from boules produced by the modified sublimation method. Wafers with tilt angles less than 0.5 deg yielded 3C-SiC; tilt angles of 3 to 4 deg resulted in 6H-SiC films. The surface morphology of these films, up to 24 microns thick, were investigated as a function of growth parameters such as the Si/C ratio in the input gases and the presence of dopant materials such as nitrogen and trimethylaluminum.

Powell, J. A.↗

NASA NTRS1994

Making Porous Luminescent Regions In Silicon Wafers

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.↗

NASA NTRS1993

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Powell, J. Anthony↗

NASA NTRS1996

Magnetically Suspended Linear Pulse Motor for Semiconductor Wafer Transfer in Vacuum Chamber

This paper describes a magnetically suspended linear pulse motor for a semiconductor wafer transfer robot in a vacuum chamber. The motor can drive a wafer transfer arm horizontally without mechanical contact. In the construction of the magnetic suspension system, four pairs of linear magnetic bearings for the lift control are used for the guidance control as well. This approach allows us to make the whole motor compact in size and light in weight. The tested motor consists of a double-sided stator and a transfer arm with a width of 50 mm and a total length of 700 mm. The arm, like a ladder in shape, is designed as the floating element with a tooth width of 4 mm (a tooth pitch of 8 mm). The mover mass is limited to about 1.6 kg by adopting such an arm structure, and the ratio of thrust to mover mass reaches to 3.2 N/kg under a broad air gap (1 mm) between the stator teeth and the mover teeth. The performance testing was carried out with a transfer distance less than 450 mm and a transfer speed less than 560 mm/s. The attitude of the arm was well controlled by the linear magnetic bearings with a combined use, and consequently the repeatability on the positioning of the arm reached to about 2 micron. In addition, the positioning accuracy was improved up to about 30 micron through a compensation of the 128-step wave current which was used for the micro-step drive with a step increment of 62.5 micron.

Moriyama, Shin-Ichi↗

NASA NTRS1997

Computational Modeling in Plasma Processing for 300 mm Wafers

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Meyyappan, Meyya↗

NASA NTRS2002

Novel On-wafer Radiation Pattern Measurement Technique for MEMS Actuator Based Reconfigurable Patch Antennas

The paper presents a novel on-wafer, antenna far field pattern measurement technique for microelectromechanical systems (MEMS) based reconfigurable patch antennas. The measurement technique significantly reduces the time and the cost associated with the characterization of printed antennas, fabricated on a semiconductor wafer or dielectric substrate. To measure the radiation patterns, the RF probe station is modified to accommodate an open-ended rectangular waveguide as the rotating linearly polarized sampling antenna. The open-ended waveguide is attached through a coaxial rotary joint to a Plexiglas(Trademark) arm and is driven along an arc by a stepper motor. Thus, the spinning open-ended waveguide can sample the relative field intensity of the patch as a function of the angle from bore sight. The experimental results include the measured linearly polarized and circularly polarized radiation patterns for MEMS-based frequency reconfigurable rectangular and polarization reconfigurable nearly square patch antennas, respectively.

Simons, Rainee N.↗

NASA NTRS2000

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Non-NASA Center↗

NASA NTRS1983

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Anthony, Thomas R.↗

NASA NTRS2004

A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Horowitz, Stephen↗

NASA NTRS2009

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Calaway, Michael J.↗

NASA NTRS2010

X-Ray Diffraction Wafer Mapping Method for Rhombohedral Super-Hetero-Epitaxy

A new X-ray diffraction (XRD) method is provided to acquire XY mapping of the distribution of single crystals, poly-crystals, and twin defects across an entire wafer of rhombohedral super-hetero-epitaxial semiconductor material. In one embodiment, the method is performed with a point or line X-ray source with an X-ray incidence angle approximating a normal angle close to 90 deg, and in which the beam mask is preferably replaced with a crossed slit. While the wafer moves in the X and Y direction, a narrowly defined X-ray source illuminates the sample and the diffracted X-ray beam is monitored by the detector at a predefined angle. Preferably, the untilted, asymmetric scans are of {440} peaks, for twin defect characterization.

Park, Yoonjoon↗

NASA NTRS2012

On-Wafer Measurement of a Multi-Stage MMIC Amplifier with 10 dB of Gain at 475 GHz

JPL has measured and calibrated a WR2.2 waveguide wafer probe from GGB Industries in order to allow for measurement of circuits in the 325-500 GHz range. Circuits were measured, and one of the circuits exhibited 10 dB of gain at 475 GHz. The MMIC circuit was fabricated at Northrop Grumman Corp. (NGC) as part of a NASA Innovative Partnerships Program, using NGC s 35-nm-gatelength InP HEMT process technology. The chip utilizes three stages of HEMT amplifiers, each having two gate fingers of 10 m in width. The circuits use grounded coplanar waveguide topology on a 50- m-thick substrate with through substrate vias. Broadband matching is achieved with coplanar waveguide transmission lines, on-chip capacitors, and open stubs. When tested with wafer probing, the chip exhibited 10 dB of gain at 475 GHz, with over 9 dB of gain from 445-490 GHz. Low-noise amplifiers in the 400-500 GHz range are useful for astrophysics receivers and earth science remote sensing instruments. In particular, molecular lines in the 400-500 GHz range include the CO 4-3 line at 460 GHz, and the CI fine structure line at 492 GHz. Future astrophysics heterodyne instruments could make use of high-gain, low-noise amplifiers such as the one described here. In addition, earth science remote sensing instruments could also make use of low-noise receivers with MMIC amplifier front ends. Present receiver technology typically employs mixers for frequency down-conversion in the 400-500 GHz band. Commercially available mixers have typical conversion loss in the range of 7-10 dB with noise figure of 1,000 K. A low-noise amplifier placed in front of such a mixer would have 10 dB of gain and lower noise figure, particularly if cooled to low temperature. Future work will involve measuring the noise figure of this amplifier.

Samoska, Lorene A.↗

NASA NTRS2014

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Microelectronics↗