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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

Refractory Oxidative-Resistant Ceramic Carbon Insulation

High-temperature, lightweight, ceramic carbon insulation is prepared by coating or impregnating a porous carbon substrate with a siloxane gel derived from the reaction of an organodialkoxy silane and an organotrialkoxy silane in an acid or base medium in the presence of the carbon substrate. The siloxane gel is subsequently dried on the carbon substrate to form a ceramic carbon precursor. The carbon precursor is pyrolyzed, in an inert atmosphere, to form the ceramic insulation containing carbon, silicon, and oxygen. The carbon insulation is characterized as a porous, fibrous, carbon ceramic tile which is particularly useful as lightweight tiles for spacecraft.

Leiser, Daniel B.↗
NASA NTRS2011

Infrared-Bolometer Arrays with Reflective Backshorts

Integrated circuits that incorporate square arrays of superconducting-transition- edge bolometers with optically reflective backshorts are being developed for use in image sensors in the spectral range from far infrared to millimeter wavelengths. To maximize the optical efficiency (and, thus, sensitivity) of such a sensor at a specific wavelength, resonant optical structures are created by placing the backshorts at a quarter wavelength behind the bolometer plane. The bolometer and backshort arrays are fabricated separately, then integrated to form a single unit denoted a backshort-under-grid (BUG) bolometer array. In a subsequent fabrication step, the BUG bolometer array is connected, by use of single-sided indium bump bonding, to a readout device that comprises mostly a superconducting quantum interference device (SQUID) multiplexer circuit. The resulting sensor unit comprising the BUG bolometer array and the readout device is operated at a temperature below 1 K. The concept of increasing optical efficiency by use of backshorts at a quarter wavelength behind the bolometers is not new. Instead, the novelty of the present development lies mainly in several features of the design of the BUG bolometer array and the fabrication sequence used to implement the design. Prior to joining with the backshort array, the bolometer array comprises, more specifically, a square grid of free-standing molybdenum/gold superconducting-transition-edge bolometer elements on a 1.4- m-thick top layer of silicon that is part of a silicon support frame made from a silicon-on-insulator wafer. The backshort array is fabricated separately as a frame structure that includes support beams and contains a correspond - ing grid of optically reflective patches on a single-crystal silicon substrate. The process used to fabricate the bolometer array includes standard patterning and etching steps that result in the formation of deep notches in the silicon support frame. These notches are designed to interlock with the support beams on the backshort-array structure to provide structural support and precise relative positioning. The backshort-array structure is inserted in the silicon support frame behind the bolometer array, and the notches in the frame serve to receive the support beams of the backshort-array structure and thus determine the distance between the backshort and bolometer planes. The depth of the notches and, thus, the distance between the backshort and bolometer planes, can be tailored to a value between 25 to 300 m adjusting only a few process steps. The backshort array is designed so as not to interfere with the placement of indium bumps for subsequent indium bump-bonding to the multiplexing readout circuitry

Miller, Timothy M.↗
NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗
NASA NTRS2004

A New Process for Fabricating Random Silicon Nanotips

An improved process for the fabrication of random arrays of silicon nanotips has been demonstrated to be feasible. Relative to other such processes, this process offers advantages of low cost and simplicity. Moreover, this process can readily be combined with other processes used to fabricate integrated circuits and other monolithic silicon structures. Arrays of silicon nanotips are subjects of research and development efforts directed toward utilizing them as field emitters in flat-panel displays, vacuum microelectronics, and microwave devices. Other silicon-nanotip-fabrication processes developed thus far predominantly include lithography, etching, and/or elaborate deposition steps followed by oxide sharpening steps and are both process intensive as well as expensive. In addition to being cheaper and simpler, the present process can efficiently produce silicon nanotips that range in height from a few microns to several tens of microns and are distributed over large areas. The process mentioned here can be summarized as consisting of (1) the growth of micro-etch masks on a silicon substrate, followed by (2) etching away of the masks, along with some of the substrate, to make an array of sharp tips. In the first step of the process, a cleaned silicon substrate is subjected to reactive ion etching (RIE) in a certain mixture of oxygen and carbon tetrafluoride under radio-frequency excitation. This process step results in the growth of fluorine based compounds in the form of stumps randomly distributed on the substrate. These stumps are known in the art as polymer RIE grass. The dimensions of these stumps are of the order of hundreds of nanometers, the exact values depending on process time and gas composition. The areal density of the stumps decreases with increasing process time as they grow and merge with neighboring stumps. These stumps constitute the micro-etch masks for the next step of the process. In the second step of the process, the substrate covered with the microetch masks is subjected to deep reactive ion etching (DRIE) process, which consists of cycles of reactive ion etching alternating with passivation (the Bosch process). The gas used in the etching substeps is sulfur hexafluoride (SF6); the gas used in the passivation substeps is octafluorocyclobutane (C4F8). The portions of the substrate directly under the RIE grass stubs are etched more slowly than are the portions between the stubs. Hence, what remains at the end of the process, after the stubs and parts of the substrate have been etched away, are silicon spikes where the stubs were (see figure). In a variation of the process, one starts with a silicon or silicon-on-insulator substrate with the intent to etch through the full thickness of the substrate. That is to say, one chooses the thickness so that the DRIE step releases individual nanotips. Such individual silicon nanotips may have utility as microscopic probes in biomedical applications.

Manohara, Harish↗
NASA NTRS1997

Characterization of Semiconductor Materials Using AOTF Instruments

A non-invasive characterization of silicon-on-insulator (SOI) wafers using white light interference measured by an AOTF polarimetric hyperspectral imaging instrument will be presented an an illustration of the technology potential. Experiments provided high resolution thickness maps of both silicon and oxide layers with accuracy and observed optically active imperfections and distributions in the structure.

polarimetric hyperspectral imaging silicon oxide↗
DOE OSTI2025

Entanglement of a nuclear spin qubit register in silicon photonics

Colour centres provide an optical interface to quantum registers based on electron and nuclear spin qubits in solids. The T centre in silicon is an emerging spin–photon interface that combines telecom O-band optical transitions and an electron spin in a scalable photonics platform. Here, in this study, we integrate T centres into single-mode photonic waveguides in a silicon-on-insulator platform. We demonstrate the initialization, coherent control and state read-out of a three-qubit register based on the electron spin of a T centre coupled to a hydrogen and a silicon nuclear spin. The spin register exhibits spin echo coherence times of 0.41(2) ms for the electron spin, 112(12) ms for the hydrogen nuclear spin and 67(7) ms for the silicon nuclear spin. We use nuclear–nuclear two-qubit gates to generate entanglement between the two nuclear spins with a fidelity of F = 0.77(3) and a coherence time of ${T}_{2}^{* }=2.60(8)$ ms. Our results show that a T centre in silicon photonics can realize a multi-qubit register with an optical interface for quantum communication.

Song, Hanbin [Lawrence Berkeley National Laborator↗
NASA NTRS2013

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Toda, Risaku↗
NASA NTRS2007

Design and Fabrication Highlights Enabling a 2 mm, 128 Element Bolometer Array for GISMO

The Backshort-Under-Grid (BUG) superconducting bolometer array architecture is intended to be highly versatile, operating in a large range of wavelengths and background conditions. We have undertaken a three-year program to develop key technologies and processes required to build kilopixel arrays. To validate the basic array design and to demonstrate its applicability for future kilopixel arrays, we have chosen to demonstrate a 128 element bolometer array optimized for 2 mm wavelength using a newly built Goddard instrument, GISMO (Goddard /RAM Superconducting 2-millimeter Observer). The arrays are fabricated using batch wafer processing developed and optimized for high pixel yield, low noise, and high uniformity. The molybdenum-gold superconducting transition edge sensors are fabricated using batch sputter deposition and are patterned using dry etch techniques developed at Goddard. With a detector pitch of 2 mm 8x16 array for GISMO occupies nearly one half of the processing area of a 100 mm silicon-on-insulator starting wafer. Two such arrays are produced from a single wafer along with witness samples for process characterization. To provide thermal isolation for the detector elements, at the end of the process over 90% of the silicon must be removed using deep reactive ion etching techniques. The electrical connections for each bolometer element are patterned on the top edge of the square grid supporting the array. The design considerations unique to GISMO, key fabrication challenges, and laboratory experimental results will be presented.

Allen, Christine↗
DOE OSTI2020

Fabrication of OMT-Coupled Kinetic Inductance Detector for CMB Detection

Future cosmic microwave background (CMB) experiments, including the large scale ground-based Stage Four CMB Experiment (CMB-S4), satellites, and balloons, aim to map the CMB to an unprecedented precision in order to answer several key questions in cosmology. However, to reach the target noise sensitivity, more than 100,000 detectors will be needed. Arrays of kinetic inductance detectors (KIDs) are a promising alternative for experiments that require large number of detectors due to the intrinsic multiplexing capabilities. We present the fabrication procedure for a prototype planar orthomode transducer (OMT)-coupled multi-color KID array optimized for 220/270 GHz frequency bands. These devices are made from silicon-on-insulator wafers to provide a low-loss substrate for the KIDs. The OMT couples the two polarizations of light from a wide-band feedhorn to separate Nb/SiN/Nb microstrip lines, which are then coupled to Al/Nb lumped-element KIDs (LEKIDs). The silicon on the backside of the OMT is etched away using deep reactive ion etch to release the OMT membrane to enable operation over a wide bandwidth. Finally, the buried oxide is removed underneath the KID capacitors in order to minimize two-level system noise and loss mitigation. We achieved a good yield (> 80%) on our prototype devices.

47 OTHER INSTRUMENTATION↗
NASA NTRS2009

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗
NASA NTRS1995

Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

Tu, Juliana↗
NASA NTRS2018

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

Denis, Kevin L.↗
NASA NTRS2009

Improved Starting Materials for Back-Illuminated Imagers

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Pain, Bedabrata↗
NASA NTRS2002

Charge-coupled device for low background observations

A charge-coupled device with a low-emissivity metal layer located between a sensing layer and a substrate provides reduction in ghost images. In a typical charge-coupled device of a silicon sensing layer, a silicon dioxide insulating layer, with a glass substrate and a metal carrier layer, a near-infrared photon, not absorbed in the first pass, enters the glass substrate, reflects from the metal carrier, thereby returning far from the original pixel in its entry path. The placement of a low-emissivity metal layer between the glass substrate and the sensing layer reflects near infrared photons before they reach the substrate so that they may be absorbed in the silicon nearer the pixel of their points of entry so that the reflected ghost image is coincident with the primary image for a sharper, brighter image.

Loh, Edwin D.↗
DOE OSTI2023

Electro-optic transduction in silicon via gigahertz-frequency nanomechanics

Interfacing electronics with optical fiber networks is key to the long-distance transfer of classical and quantum information. Piezo-optomechanical transducers enable such interfaces by using gigahertz-frequency acoustic vibrations as mediators for converting microwave photons to optical photons via the combination of optomechanical and piezoelectric interactions. However, despite successful demonstrations, efficient quantum transduction remains out of reach due to the challenges associated with hybrid material integration and increased loss from piezoelectric materials when operating in the quantum regime. Here, we demonstrate an alternative approach in which we actuate 5-GHz phonons in a conventional silicon-on-insulator platform. In our experiment, microwave photons resonantly drive a phononic crystal oscillator via the electrostatic force realized in a charge-biased narrow-gap capacitor. The mechanical vibrations are subsequently transferred via a phonon waveguide to an optomechanical cavity, where they transform into optical photons in the sideband of a pump laser field. Operating at room temperature and atmospheric pressure, we measure a microwave-to-optical photon conversion efficiency of 1.72±0.14×10 −7 in a 3.3 MHz bandwidth. Our results mark a stepping stone towards quantum transduction with integrated devices made from crystalline silicon, which promise efficient high-bandwidth operation and integration with superconducting qubits. Additionally, the lack of need for piezoelectricity or other intrinsic nonlinearities makes our approach applicable to a wide range of materials for potential applications beyond quantum technologies.

42 ENGINEERING↗
DOE OSTI2026

Slow-Light Mid-IR Silicon Photonic Chips for NO 2 and CH 4 Gas Detection

A compact, chip-scale mid-infrared gas sensor is demonstrated, leveraging a two-dimensional photonic crystal waveguide (PCW) fabricated on a silicon-on-insulator (SOI) platform. The PCW comprises a hexagonal lattice with lattice constant a = 860 nm and hole radius r = 0.22a, incorporating a central line defect of reduced-radius holes (r s = 0.7r) to induce slow-light propagation near the photonic band edge with a group index of approximately 73, thereby enhancing light-matter interaction. The sensor operates at fundamental absorption wavelengths of 3.42 μm for nitrogen dioxide (NO 2 ) and 3.40 μm for methane (CH 4 ), utilizing the strongest molecular vibrational transitions for maximum sensitivity. Experimental validation was conducted using dynamically diluted gas mixtures generated by mass flow controllers, with signal acquisition performed by a liquid nitrogen-cooled InSb detector. For NO 2 , the sensor exhibited excellent linear response over 5–25 ppm (part per million) with coefficient of determination R 2 = 0.9934, achieving a detection limit of 210 ppb (part per billion)─representing the first reported silicon photonic-based NO 2 detection. For CH 4 , exposure to 25 ppm resulted in a 6.4% decrease in transmitted intensity, demonstrating multigas sensing capability. The CMOS-compatible fabrication process and compact 3 mm device footprint establish this SOI-PCW platform as a scalable, low-power solution for integrated mid-infrared gas sensing, with significant potential for environmental monitoring and industrial safety applications.

Crystals↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2024

Isolation of individual Er quantum emitters in anatase TiO 2 on Si photonics

Defects and dopant atoms in solid state materials are a promising platform for realizing single photon sources and quantum memories, which are the basic building blocks of quantum repeaters needed for long distance quantum networks. In particular, trivalent erbium (Er 3+ ) is of interest because it couples C-band telecom optical transitions with a spin-based memory platform. In order to produce quantum repeaters at the scale required for quantum networks it is imperative to integrate these necessary building blocks with mature and scalable semiconductor processes. Here, in this work, we demonstrate the optical isolation of single Er 3+ ions in CMOS-compatible titanium dioxide (TiO 2 ) thin films monolithically integrated on a silicon-on-insulator photonics platform. Our results demonstrate an initial step toward the realization of a monolithically integrated and scalable quantum photonics package based on Er 3+ doped thin films.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗