Results for “SiC devices” — Page 5

NASA NTRS1998

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (less than 250 V) 4H-SiC p(+)n Junction diodes: DC Properties - Part 1

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = 1c with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4)/sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗

NASA NTRS1999

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (<250 V) 4H-SiC p+n Junction Diodes - Part 1: DC Properties

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = lc with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4) sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗

DOE OSTI2021

Advances in High-Resolution Radiation Detection Using 4H-SiC Epitaxial Layer Devices

Explore the source record for details and available documents.

99 GENERAL AND MISCELLANEOUS↗

DOE OSTI2021

Characterization of Highly Thermally Conductive Organic Substrates for a Double-Sided Cooled Power Module

Abstract Silicon-Carbide (SiC) power devices have become a promising option for traditional Silicon (Si) due to the superior material properties. To fully take advantage of the SiC devices, a high-performance power device packaging solution is necessary. This study proposes a cost-effective double-sided cooled (DSC) 1.2 kV SiC half-bridge power module using organic epoxy-resin composite dielectric (ERCD) substrates. The high mechanical and thermal performance of the power module is achieved by the low-modulus, moderate thermal conductivity, and relatively thin (120 μm) layer of ERCD material compared with traditional metal-clad ceramic approaches. This novel organic dielectric can withstand high voltage (5 kV @ 120 μm) and operate up to 250°C continuously, which is indispensable for high power applications. The thermal modeling results show that the equivalent thermal resistance junction-to-case (Rjc_eq) of the DSC power module using dual direct bonded copper (DBC) is 17% higher than the dual ERCD configuration. Furthermore, a non-insulated DSC power module concept is proposed for maximizing thermal performance by considering thermal vias in the ERCD substrate and direct-soldered heat sink. A thought process for optimization of thermal via design is demonstrated and it shows up to 24% of improvement on thermal performance compared with the insulated DSC power module.

Double-sided cooling, epoxy-resin composite dielec↗

NASA NTRS2001

Thermally Stable Ohmic Contacts on Silicon Carbide Developed for High- Temperature Sensors and Electronics

The NASA aerospace program, in particular, requires breakthrough instrumentation inside the combustion chambers of engines for the purpose of, among other things, improving computational fluid dynamics code validation and active engine behavioral control (combustion, flow, stall, and noise). This environment can be as high as 600 degrees Celsius, which is beyond the capability of silicon and gallium arsenide devices. Silicon-carbide- (SiC-) based devices appear to be the most technologically mature among wide-bandgap semiconductors with the proven capability to function at temperatures above 500 degrees Celsius. However, the contact metalization of SiC degrades severely beyond this temperature because of factors such as the interdiffusion between layers, oxidation of the contact, and compositional and microstructural changes at the metal/semiconductor interface. These mechanisms have been proven to be device killers. Very costly and weight-adding packaging schemes that include vacuum sealing are sometimes adopted as a solution.

Okojie, Robert S.↗

NASA NTRS2003

Silicon Carbide Diodes Performance Characterization and Comparison With Silicon Devices

Commercially available silicon carbide (SiC) Schottky diodes from different manufacturers were electrically tested and characterized at room temperature. Performed electrical tests include steady state forward and reverse I-V curves, as well as switching transient tests performed with the diodes operating in a hard switch dc-to-dc buck converter. The same tests were performed in current state of the art silicon (Si) and gallium arsenide (GaAs) Schottky and pn junction devices for evaluation and comparison purposes. The SiC devices tested have a voltage rating of 200, 300, and 600 V. The comparison parameters are forward voltage drop at rated current, reverse current at rated voltage and peak reverse recovery currents in the dc to dc converter. Test results show that steady state characteristics of the tested SiC devices are not superior to the best available Si Schottky and ultra fast pn junction devices. Transient tests reveal that the tested SiC Schottky devices exhibit superior transient behavior. This is more evident at the 300 and 600 V rating where SiC Schottky devices showed drastically lower reverse recovery currents than Si ultra fast pn diodes of similar rating.

Lebron-Velilla, Ramon C.↗

NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗

NASA NTRS2008

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗

NASA NTRSDate not supplied

DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.

4H-SiC JFET↗

NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗

NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗

NASA NTRS2006

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗

NASA NTRS2007

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗

NASA NTRS2018

Cryogenic Parametric Characterization of Gallium Nitride Switches

This report presents the parametric characterization results of four GaN field-effect transistor (FET) devices from three manufacturers, one of which is a cascode device, and compares those results to a Si power metal-oxide-semiconductor fieldeffect transistor (MOSFET) and a SiC power MOSFET. The devices were first characterized at ambient temperature, then at cryogenic temperatures down to -196 C (LN2 temperature), and finally at ambient temperature again in the event that the device parameters were permanently affected by the cryogenic temperatures. In general, the results indicate that the GaN devices show significant improvement overall at cryogenic temperatures in the parameters characterized, such as onresistance and leakage currents, compared to the Si and SiC devices. The results show that the SiC device tested should not be used at cryogenic temperatures due to the significant increase in on-resistance. The results also show that the GaN and Si parameters characterized were either not affected by the cryogenic temperatures or changed by no more than +/-20 percent post LN2 submersion. The device that exhibited the most parametric change post LN2 submersion was the SiC power MOSFET in its leakage currents.

Gonzalez, Marcelo C.↗

NASA NTRS2004

Step Free Surface Heteroepitaxy of 3C-SiC Layers on Patterned 4H/6H-SiC Mesas and Cantilevers

The off-axis approach to SiC epitaxial growth has not prevented many substrate crystal defects from propagating into SiC epilayers, and does not permit the realization of SiC heteropolytype devices. This paper reviews recent advancements in SiC epitaxial growth that begin to overcome the above shortcomings for arrays of device-sized mesas patterned into on-axis 4H/6HSiC wafers. These on-axis mesa growth techniques have produced 4H/6H-SiC homoepilayers and 3C-SiC heteroepilayers with substantially lower dislocation densities. The results should enable improved homojunction and heterojunction silicon carbide prototype devices.

Neudeck, P. G.↗

NASA NTRS2007

Growth and Characterization of 3C-SiC and 2H-AIN/GaN Films and Devices Produced on Step-Free 4H-SiC Mesa Substrates

While previously published experimental results have shown that the step-free (0 0 0 1) 4H-SiC mesa growth surface uniquely enables radical improvement of 3C-SiC and 2H-AlN/GaN heteroepitaxial film quality (greater than 100-fold reduction in extended defect densities), important aspects of the step-free mesa heterofilm growth processes and resulting electronic device benefits remain to be more fully elucidated. This paper reviews and updates recent ongoing studies of 3C-SiC and 2H-AlN/GaN heteroepilayers grown on top of 4H-SiC mesas. For both 3C-SiC and AlN/GaN films nucleated on 4H-SiC mesas rendered completely free of atomic-scale surface steps, TEM studies reveal that relaxation of heterofilm strain arising from in-plane film/substrate lattice constant mismatch occurs in a remarkably benign manner that avoids formation of threading dislocations in the heteroepilayer. In particular, relaxation appears to occur via nucleation and inward lateral glide of near-interfacial dislocation half-loops from the mesa sidewalls. Preliminary studies of homojunction diodes implemented in 3C-SiC and AlN/GaN heterolayers demonstrate improved electrical performance compared with much more defective heterofilms grown on neighbouring stepped 4H-SiC mesas. Recombination-enhanced dislocation motion known to degrade forward-biased 4H-SiC bipolar diodes has been completely absent from our initial studies of 3C-SiC diodes, including diodes implemented on defective 3C-SiC heterolayers grown on stepped 4H-SiC mesas.

Neudeck, P. G.↗

DOE OSTI2021

Record-Low Thermal Boundary Resistance between Diamond and GaN-on-SiC for Enabling Radiofrequency Device Cooling

The implementation of 5G-and-beyond networks requires faster, high-performance, and power-efficient semiconductor devices, which are only possible with materials that can support higher frequencies. Gallium nitride (GaN) power amplifiers are essential for 5G-and-beyond technologies since they provide the desired combination of high frequency and high power. These applications along with terrestrial hub and backhaul communications at high power output can present severe heat removal challenges. The cooling of GaN devices with diamond as the heat spreader has gained significant momentum since device self-heating limits GaN’s performance. However, one of the significant challenges in integrating polycrystalline diamond on GaN devices is maintaining the device performance while achieving a low diamond/GaN channel thermal boundary resistance. In this study, we achieved a record-low thermal boundary resistance of around 3.1 ± 0.7 m 2 K/GW at the diamond/Si 3 N 4 /GaN interface, which is the closest to theoretical prediction to date. The diamond was integrated within ~1 nm of the GaN channel layer without degrading the channel’s electrical behavior. Furthermore, we successfully minimized the residual stress in the diamond layer, enabling more isotropic polycrystalline diamond growth on GaN with thicknesses >2 μm and a ~1.9 μm lateral grain size. More isotropic grains can spread the heat in both vertical and lateral directions efficiently. Using transient thermoreflectance, the thermal conductivity of the grains was measured to be 638 ± 48 W/m K, which when combined with the record-low thermal boundary resistance makes it a leading-edge achievement.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

NASA NTRS1999

Electrical Impact of SiC Structural Crystal Defects on High Electric Field Devices (Invited)

As illustrated by the invited paper at this conference and other works, SiC wafers and epilayers contain a variety of crystallographic imperfections, including micropipes, closed-core screw dislocations, grain boundaries, basal plane dislocations, heteropolytypic inclusions, and surfaces that are often damaged and contain atomically rough features like step bunching and growth pits or hillocks. Present understanding of the operational impact of various crystal imperfections on SiC electrical devices is reviewed, with an emphasis placed on high-field SiC power devices and circuits.

Neudeck, Philip G.↗