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All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

CCSDS Time-Critical Onboard Networking Service

The Consultative Committee for Space Data Systems (CCSDS) is developing recommendations for communication services onboard spacecraft. Today many different communication buses are used on spacecraft requiring software with the same basic functionality to be rewritten for each type of bus. This impacts on the application software resulting in custom software for almost every new mission. The Spacecraft Onboard Interface Services (SOIS) working group aims to provide a consistent interface to various onboard buses and sub-networks, enabling a common interface to the application software. The eventual goal is reusable software that can be easily ported to new missions and run on a range of onboard buses without substantial modification. The system engineer will then be able to select a bus based on its performance, power, etc and be confident that a particular choice of bus will not place excessive demands on software development. This paper describes the SOIS Intra-Networking Service which is designed to enable data transfer and multiplexing of a variety of internetworking protocols with a range of quality of service support, over underlying heterogeneous data links. The Intra-network service interface provides users with a common Quality of Service interface when transporting data across a variety of underlying data links. Supported Quality of Service (QoS) elements include: Priority, Resource Reservation and Retry/Redundancy. These three QoS elements combine and map into four TCONS services for onboard data communications: Best Effort, Assured, Reserved, and Guaranteed. Data to be transported is passed to the Intra-network service with a requested QoS. The requested QoS includes the type of service, priority and where appropriate, a channel identifier. The data is de-multiplexed, prioritized, and the required resources for transport are allocated. The data is then passed to the appropriate data link for transfer across the bus. The SOIS supported data links may inherently provide the quality of service support requested by the intra-network layer. In the case where the data link does not have the required level of support, the missing functionality is added by SOIS. As a result of this architecture, re-usable software applications can be designed and used across missions thereby promoting common mission operations. In addition, the protocol multiplexing function enables the blending of multiple onboard networks. This paper starts by giving an overview of the SOIS architecture in section 11, illustrating where the TCONS services fit into the overall architecture. It then describes the quality of service approach adopted, in section III. The prototyping efforts that have been going on are introduced in section JY. Finally, in section V the current status of the CCSDS recommendations is summarized.

Parkes, Steve↗
NASA NTRS2013

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Toda, Risaku↗
NASA NTRS1982

Global pictures of the ozone field from high altitudes from DE-I

Detailed synoptic views of the column ozone field can be obtained by the Spin-Scan Ozone Imager (SOI) (Keating et al., 1981) aboard the Dynamics Explorer I satellite. The eccentric polar orbit with an apogee altitude of 23,000 km allows high resolution global-scale images to be obtained within 12 minutes, and allows regions to be viewed for long periods of time. At perigee, a pixel size of nadir measurements of 3 km is possible, and measurements are determined using the backscattered ultraviolet technique. A wavelength measurement of 317.5 nm is used as there are limitations in filter locations and it allows comparison with Nimbus 7 SBUV/TOMS data. Consideration of the reflectivities of this data aids in checking the SOI data reduction algorithm. SOI data show short-term (less than one day) variations in the observed ozone field, and a negative correlation (greater than 0.9) between ozone and tropopause heights. It is expected, due to this correlation, that SOI data will aid in understanding the time evolution of dynamics near the tropopause.

Keating, G. M.↗
NASA NTRS1987

Calibration of the spin-scan ozone imager aboard the dynamics Explorer 1 satellite

The calibration technique, which contains the calibrated backscattered radiance values necessary for performing the calibrations, is presented. The calibration constants for September to October 1981 to determine total columnar ozone from the Spin-Scan Ozone Imager (SOI), which is a part of the auroral imaging instrumentation aboard the Dynamics Explorer 1 Satellite, are provided. The precision of the SOI-derived total columnar ozone is estimated to be better than 2.4 percent. Linear regression analysis was used to calculate correlation coefficients between total columnar ozone obtained from Dobson ground stations and SOI which indicate that the SOI total columnar ozone determination is equally accurate for clear or cloudy weather conditions.

Bressette, Walter E.↗
NASA NTRS1992

Canadian Space Agency Space Station Freedom utilization plans

Under the terms of the NASA/CSA Memorandum of Understanding, Canada will contribute the Mobile Servicing System and be entitled to use 3 percent of all Space Station utilization resources and user accommodations over the 30 year life of the Station. Equally importantly Canada, like NASA, can begin to exploit these benefits as soon as the Man-Tended Capability (MTC) phase begins, in early 1997. Canada has been preparing its scientific community to fully utilize the Space Station for the past five years; most specifically by encouraging, and providing funding, in the area of Materials Science and Applications, and in the area of Space Life Sciences. The goal has been to develop potential applications and an experienced and proficient Canadian community able to effectively utilize microgravity environment facilities such as Space Station Freedom. In addition, CSA is currently supporting four facilities; a Laser Test System, a Large Motion Isolation Mount, a Canadian Float Zone Furnace, and a Canadian Protein Crystallization Apparatus. In late April of this year CSA sent out a Solicitation of Interest (SOI) to potential Canadian user from universities, industry, and government. The intent of the SOI was to determine who was interested, and the type of payloads which the community at large intended to propose. The SOI will be followed by the release of an Announcement of Opportunity (AO) following governmental approval of the Long Term Space plan later this year, or early next year. Responses to the AO will be evaluated and prioritized in a fair and impartial payload selection process, within the guidelines set by our international partners and the Canadian Government. Payload selection is relatively simple compared to the development and qualification process. An end-to-end user support program is therefore also being defined. Much of this support will be provided at the new headquarters currently being built in St. Hubert, Quebec. It is recognized that utilizing the Space Station could be expensive for users; costing in many cases millions of dollars to get a payload from conception to retrieval. It is also recognized that some of the potential users cannot or will not invest a lot of money or effort into Space Station utilization, unless there is a perceived significant commercial potential. How best to fund Space Station payloads is under study. Space Station Freedom will provide the first opportunity for Canada to conduct experiments in a long-duration microgravity environment. CSA have been developing and funding potential users for some time, and considerable interest has been shown by the response to our SOI earlier this year. Canada can be one of the two earliest users for the Space Station, along with NASA. We hope to take full advantage of this opportunity.

Faulkner, James↗
NASA NTRS2004

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

single event upset (SEU)↗
NASA NTRS2008

GSFC Technical Outreach: The Capitol College Model

In February 2005, as part of the National Aeronautic and Space Administration (NASA) Technical Outreach Program, Goddard Space Flight Center (GSFC) awarded Capitol College of Laurel, Maryland an Educational Grant to establish a Space Operation academic curriculum to meet the future needs of mission operations engineers. This was in part due to the aerospace industry and GSFC concerns that a large number of professional engineers are projected to retire in the near term with evidence showing that current enrollment in engineering schools will not produce sufficient number of space operation trained engineers that will meet industry and government demands. Capitol College, under the agreement of the Educational Grant, established the Space Operations Institute (SOI) with a new curriculum in Space Operations that was approved and certified by the State of Maryland. The SO1 programs focuses on attracting, recruiting, and training a pipeline of highly qualified engineers with experience in mission operations, system engineering and development. The selected students are integrated as members of the engineering support team in any of the missions supported by the institute. The students are mentored by professional engineers from several aerospace companies that support GSFC. Initially, the institute was involved in providing console engineers and mission planning trainees for the Upper Atmosphere Research Satellite (UARS), the Earth Radiation Budget Satellite (ERBS) and the Total Ozone Mapping Spectrometer mission (TOMS). Subsequently, the students were also involved in the technology refresh of the TOMS ground system and other mission operations development. Further mission assignment by GSFC management included participation in the Tropical Rainfall Measuring Mission (TRMM) mission operations and ground system technology refresh. The SOI program has been very successful. Since October 2005, sixty-four students have been enrolled in the SOI program and twenty-five have already graduated from the program, nineteen of whom are employed by company's supporting GSFC. Due to the success of the program, the initial grant period was extended for another period of two years. This paper presents the process that established the SOI as a viable pipeline of mission operations engineers, the lessons learned in the process of dealing with grants, and experience gained in mentoring engineering students that are responsible for particular areas of expertise and functionality. This paper can also be considered a case study and model for integrating a student team with government and industry professionals in the real world of mission operations.

Marius, Julio L.↗
NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗
NASA NTRS2005

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Kaul, Anupama↗
NASA NTRS2010

A National Partnership-Based Summer Learning Initiative to Engage Underrepresented Students with Science, Technology, Engineering and Mathematics

In response to the White House Educate to Innovate campaign, NASA developed a new science, technology, engineering, and mathematics (STEM) education program for non-traditional audiences that also focused on public-private partnerships and nationwide participation. NASA recognized that summer break is an often overlooked but opportune time to engage youth in STEM experiences, and elevated its ongoing commitment to the cultivation of diversity. The Summer of Innovation (SoI) is the resulting initiative that uses NASA's unique missions and resources to boost summer learning, particularly for students who are underrepresented, underserved and underperforming in STEM. The SoI pilot, launched in June 2010, is a multi-faceted effort designed to improve STEM teaching and learning through partnership, multi-week summer learning programs, special events, a national concluding event, and teacher development. The SoI pilot features strategic infusion of NASA content and educational resource materials, sustainability through STEM Learning Communities, and assessments of effectiveness of SoI interventions with other pilot efforts. This paper examines the inception and development of the Summer of Innovation pilot project, including achievements and effectiveness, as well as lessons learned for future efforts.

Melvin, Leland↗
NASA NTRS2003

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok↗
NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A. D↗
NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan d, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 µ m thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan d with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan d ~ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan d in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· d = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· d = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A D↗
DOE OSTI2024

High Linearity RF Circuits in CMOS Platforms (CRADA Final Report)

The goal of this CRADA was to understand high linearity silicon-on-insulator (SOI) radio frequency switches. The first direction investigated was high linearity RF mixers as these components are composed of a network of switches. During the course of the investigation, it was determined that while the SOI RF switches were effective in the application in mixers and produced state of the art performance, the use of SOI for mixers is not economically feasible because the technology only worked with advanced CMOS nodes <65nm which can have an NRE cost (from lithography masks) in excess of $\$$500,000.

42 ENGINEERING↗
NASA NTRS1984

Empirical studies of upper atmospheric species

The first month of spin-scan ozone imaging (SOI) data (October 1981) was processed and compared with total ozone mapping spectrometer and ground based data. Short term variations in the ozone field have been revealed using animated sequences of SOI data. High correlations were observed between SOI ozone and upper tropospheric meteorological data. The relationship between ozone and temperature in the stratosphere was investigated by examining Nimbus 4 backscattered ultraviolet ozone and selective chopper radiometer temperature measurements as well as solar Nimbus 7 solar backscattered ultraviolet ozone and stratospheric and mesospheric sounder temperature measurements. Results from these ozone temperature studies were compared with calculations from theoretical 2-D models. All of the lims infrared monitor of the stratosphere data was processed at 10 pressure levels and correlations between various species have been performed. The Venus Atmospheric Drag model was modified taking into account recent investigations on the Venus thermosphere and the resulting model was considered for incorporation into the Venus International Reference Atmosphere.

Nicholson, J.↗
NASA NTRS1985

Excitation of the Earth's Chandler wobble by southern oscillation/El Nino, 1900-1979

The southern oscillation/El Nino (ENSO) is the single most prominent interannual signal in global atmospheric/oceanic fluctuations. The following question is addressed: how important is the angular momentum carried by ENSO in exciting the Earth's Chandler wobble? The question is attacked through a statistical analysis of the coherence spectra (correlation as a function of frequency) between two data sets spanning 1900 to 1979-the southern oscillation index (SOI) time series and the excitation function psi (with x-component psi sub x and y-component psi sub y) of the Chandler wobble derived from the homogeneous ILS (International Latitude Service) polar motion data. The coherence power and phase in the Chandler frequency band (approx. 0.79 to 0.89 cpy) are studied. It is found that, during 1900 to 1979 the coherence between SOI and psi sub x is significant well over the 95% confidence threshold whereas that between SOI and psi sub y is practically nil. Quantitatively, the coherence study shows that ENSO provides some 20% of the observed Chandler wobble excitation power. Since earlier investigations have shown that the total atmospheric/oceanic variation can account for the Chandler wobble excitation at about 20% level, the implication is that ENSO maybe an important (interannual) part of the atmospheric/oceanic variation that is responsible for the Chandler wobble excitation during 1900 to 1979.

Chao, B. F.↗
NASA NTRS1991

The Solar Oscillations Investigation-Michelson Doppler Imager for SOHO

The Solar Oscillations Investigation-Michelson Doppler Imager (SOI-MDI) for the SOHO (Solar and Heliospheric Observatory) mission is intended to investigate the solar interior using helioseismology techniques. The SOI program consists of a coordinated set of observations intended to address a set of science objectives, an MDI instrument, and a facility that will provide data reduction and analysis capability. The MDI instrument will take filtergrams to measure LOS velocity, line and continuum intensity, and LOS magnetic fields with both 4 and 1.2 arcsec resolution, The SOI study is designed to take advantage of the anticipated SOHO telemetry by organizining the observations into four programs: structure (at all times), dynamics (two months per year), campaign (eight hours per day, 10 months per year), and magnetic field (a few minutes per day).

Scherrer, P. H.↗
NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗