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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1967

Science data systems

Video film converter for data processing, linear feedback shift registers, and woven plated wire memory storage units for science missions

MEMORY STORAGE UNIT↗
NASA NTRS1982

Serial data correlator/code translator

A system for analyzing asynchronous signals containing bits of information for ensuring the validity of said signals, by sampling each bit of information a plurality of times, and feeding the sampled pieces of bits of information into a sequence controlled is described. The sequence controller has a plurality of maps or programs through which the sampled pieces of bits are stepped so as to identify the particular bit of information and determine the validity and phase of the bit. The step in which the sequence controller is clocked is controlled by a storage register. A data decoder decodes the information fed out of the storage register and feeds such information to shift registers for storage.

Morgan, L. E.↗
NASA NTRS1992

Nonlinear, nonbinary cyclic group codes

New cyclic group codes of length 2(exp m) - 1 over (m - j)-bit symbols are introduced. These codes can be systematically encoded and decoded algebraically. The code rates are very close to Reed-Solomon (RS) codes and are much better than Bose-Chaudhuri-Hocquenghem (BCH) codes (a former alternative). The binary (m - j)-tuples are identified with a subgroup of the binary m-tuples which represents the field GF(2 exp m). Encoding is systematic and involves a two-stage procedure consisting of the usual linear feedback register (using the division or check polynomial) and a small table lookup. For low rates, a second shift-register encoding operation may be invoked. Decoding uses the RS error-correcting procedures for the m-tuple codes for m = 4, 5, and 6.

Solomon, G.↗
NASA NTRS1980

Study of digital charge coupled devices

Charge coupled devices represent unique usage of the metal oxide semiconductor concept. These devices can sample an AC signal at the input, transfer charge proportional to this signal through the CCD shift register and then provide an output of the same frequency and shape as the input. The delay time between input and output is controlled by the CCD operating frequency and the number of stages in the shift resistor. This work is a reliability evaluation of the buried channel and surface channel CCD technologies. The constructions are analyzed, failure modes are described, and test results are reported.

Wilson, D. D.↗
NASA NTRS1976

Effects of neutron irradiation on the characteristics of a buried channel CCD at 80 degrees Kelvin and 295 degrees Kelvin

Buried channel CCD shift registers were irradiated with 15 MeV neutrons. The irradiations were performed at 80 K and 295 K on operating devices with normal clocks and bias voltages applied. Dark current increased from the pre-irradiation value of 7 nA/sq cm to 1,600 nA/sq cm at 1 x 10 to the 13th power n/sq cm. The input gate threshold shift observed at 80K was minus 0.9 volts per 10 to the 13th power n/sq cm, a factor of 4 less than that predicted from a first order calculation of the equivalent ionization dose of neutrons in the oxide. Transfer efficiency measurements yielded a bulk electron trap creation rate for neutron irradiation of 14.0 cm to the minus 1 power at 295 K with a trap emission time constant of 25 microseconds.

Saks, N. S.↗
NASA NTRS1989

Long period pseudo random number sequence generator

A circuit for generating a sequence of pseudo random numbers, (A sub K). There is an exponentiator in GF(2 sup m) for the normal basis representation of elements in a finite field GF(2 sup m) each represented by m binary digits and having two inputs and an output from which the sequence (A sub K). Of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs (E sub K) of maximal length shift register of n stages. There is a switch having a pair of inputs and an output. The switch outputs is connected to the other of the two inputs of the exponentiator. One of the switch inputs is connected for initially receiving a primitive element (A sub O) in GF(2 sup m). Finally, there is a delay circuit having an input and an output. The delay circuit output is connected to the other of the switch inputs and the delay circuit input is connected to the output of the exponentiator. Whereby after the exponentiator initially receives the primitive element (A sub O) in GF(2 sup m) through the switch, the switch can be switched to cause the exponentiator to receive as its input a delayed output A(K-1) from the exponentiator thereby generating (A sub K) continuously at the output of the exponentiator. The exponentiator in GF(2 sup m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U(sub i) = 92(sup i) (for n(sub i) = 1 or 1 (for n(subi) = 0).

Wang, Charles C.↗
DOE OSTI2025

Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS

One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Time-tagging data acquisition system for testing superconducting electronics based on an RFSoC and custom analog frontend

Novel electronic devices can often be operated in a plethoraof ways, which makes testing circuits comprised of them difficult.Often, no single tool can simultaneously analyze the operatingmargins, maximum speed, and failure modes of a circuit, particularlywhen the intended behavior of subcomponents of the circuit is notstandardized. This work demonstrates a cost-effective time-domaindata acquisition system for electronic circuits that enables moreintricate verification techniques than are practical withconventional experimental setups. We use high-speeddigital-to-analog converters and real-timemulti-gigasample-per-second waveform processing to push experimentalcircuits beyond their maximum operating speed. Our customtime-tagging data capture firmware reduces memory requirements andcan be used to determine when errors occur. The firmware iscombined with a thermal-noise-limited analog frontend with50 dB of dynamic range. Compared to currentlyavailable commercial test equipment that is seven times moreexpensive, this data acquisition system was able to operate asuperconducting shift register at a nearly three-times-higher clockfrequency (200 MHz vs. 80 MHz).

Foster, Reed A. [MIT] (ORCID:0000000231002127)↗
DOE OSTI2026

Characterization of Digital Silicon Photomultipliers

Digital Silicon photomultipliers (Digital SiPMs) have become an increasingly viable option for single-photon detection due to their compact size and precise timing and resolution. The following work characterizes the noise performance of a diSiPM designed and tested in-house at Fermilab. The SiPM consists of a 26x32 array of single-photon avalanche diode (SPAD) cells. Through the implementation of a shift register masking circuit, individual SPAD cells can be enabled and disabled at will, allowing for precise detection measurements of single columns (accumulator channels) and cells. The provided circuit design operates on voltage clock pulses and collects data on clock edges allowing for precise tuning of the data collection process by varying the clock frequency, pulse width, and integration period.

Shoemaker, Oliver [U. Chicago (main)]↗
NASA NTRS1965

Notes on System Theory, Volume VII

System theory - matrices, feedback control system, network synthesis, set theory, stability, shift registers, coding, theorem proving, polynomial roots, channels, and signal flow graphs

FEEDBACK CONTROL SYSTEM↗
NASA NTRS1967

Electronic frequency discriminator

Digital comparator permits discrimination at accuracy of reference frequency. The compare circuit is a shift register element.

Reid, W. J.↗
NASA NTRS1967

Teleprinter uses thermal printing technique

Alphameric/facsimile printer receives serial digital data in the form of a specified number of bits per group and prints it on thermally sensitive paper. A solid state shift-register memorizes the incoming serial digital data.

Perkins, R. D.↗