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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Printed Circuit Board Assembly for Use in Space Missions

An electronic assembly for use in space missions that includes a PCB and one or more multi-pin CGA devices coupled to the PCB. The PCB has one or more via-in-pad features and each via-in-pad feature comprises a land pad configured to couple a pin of the one or more multi-pin CGA devices to the via. The PCB also includes a plurality of layers arranged symmetrically in a two-halves configuration above and below a central plane of the PCB.

Petrick, David J.↗
NASA NTRS2016

Printed Circuit Board Quality Assurance

PCB Assurance Summary: PCB assurance actives are informed by risk in context of the Project. Lessons are being applied across Projects for continuous improvements. Newer component technologies, smaller/high pitch devices: tighter and more demanding PCB designs: Identifying new research areas. New materials, designs, structures and test methods.

Reliability↗
DOE OSTI2024

Aerosol-Jet Printed Transferable Millimeter-Wave Circuits

Printed millimeter wave (mmW) electronics have been of high interest in the field of communications for some time now due to the potential ability to fabricate mmW systems that utilize 3-Dimension Heterogeneous Integration (3DHI) to improve performance beyond traditional systems. Here, in this paper, a method for fabricating transferable mmW structures via aerosol-jet printing (AJP) is presented. A PDMS stamp assisted liftoff procedure is developed to separate the printed part from a rigid printing support surface and apply it to an adhesive target surface. Several microstrip (MS) line structures are demonstrated to characterize the effect of stamp transfer on the RF performance of the printed circuits. The effects of printed vias on RF probe pads and shifts in the resonant frequencies of a Beatty standard line after transfer are considered and characterized using S-parameter measurements.

42 ENGINEERING↗
NASA NTRS2019

Achieving Improved Reliability with Failure Analysis

Reliability is the ability of a product to properly function, within specified performance limits, for a specified period of time, under the life cycle application conditions. Failure analysis is a vital tool in the effort to ensure reliability of electronic products and systems throughout their product lifecycle. Today, organizations involved in activities within the electronics supply chain are facing new challenges, not just from complex assembly styles, harsher lifecycle environments, and sophisticated supply chains, but also from customers who are demanding a quicker turn-around. Unfortunately, root cause failure analysis is often performed incompletely, leading to a poor understanding of failure mechanisms and causes and, customer dissatisfaction due to recurring failures. The PDC (Professional Development Course) starts with an introduction to reliability concepts, physics of failure and an overview of failure mechanisms that affect PCBs (Printed Circuit Boards), PCBAs (Printed Circuit Board Assembly) and components. The PDC then dives into root cause hypothesizing techniques (Pareto, FMEA (Failure Modes and Effects Analysis), fishbone (Cause-And-Effect Diagram), FTA (Fault Tree Analysis)), non-destructive and destructive analysis and, materials characterization will be discussed. Numerous failure analysis case studies will be used to illustrate the techniques and analysis principles to arrive at the root cause(s) of field failures on printed circuit boards, active components, and assemblies. What Attendees will Learn: Topics include: Overview of Reliability Concepts Failure mechanisms of electronic products Root cause analysis Failure analysis techniques -Non-destructive techniques (optical, CSAM (Confocal Scanning Electron Microscopy) etc.) -Destructive analysis (DPA (Destructive Physical Analysis), Decap (Decapsulation), FIB (Focused Ion Beam) etc.) -Materials characterization (XRF (X-Ray Fluorescence) , EDS (Error Detection Sequential), TMA/DSC (Thermal Mechanical Analysis/Differential Scanning Calorimetry) etc.)

PCB quality↗
NASA NTRS1966

Process produces accurate registry between circuit board prints

Tapes and quick-mount circles of contrasting colors aid in obtaining precise registry between the two circuits of two-sided printed circuit boards. The tapes and circles are mounted on opposite sides of transparent plastic film to define the conductive path and feed-through hole locations.

Source record↗
NASA NTRS2009

Board Saver for Use with Developmental FPGAs

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Berkun, Andrew↗
NASA NTRS1987

Rupture testing for the quality control of electrodeposited copper interconnections in high-speed, high-density circuits

Printed Wiring Multilayer Board (PWMLB) structures for high speed, high density circuits are prone to failure due to the microcracking of electrolytic copper interconnections. The failure can occur in the foil that makes up the inner layer traces or in the plated through holes (PTH) deposit that forms the layer to layer interconnections. It is shown that there are some distinctive differences in the quality of Type E copper and that these differences can be detected before its use in a PWMLB. It is suggested that the strength of some Type E copper can be very low when the material is hot and that it is the use of this poor quality material in a PWMLB that results in PTH and inner layer microcracking. Since the PWMLB failure in question are induced by a thermal stress, and since the poorer grades of Type E materials used in these structures are susceptible to premature failure under thermal stress, the use of elevated temperature rupture and creep rupture testing is proposed as a means for screening copper foil, or its PTH equivalent, in order to eliminate the problem of Type E copper microcracking in advanced PWMLBs.

Zakraysek, Louis↗
NASA NTRS1975

Banning design automation software implementation

The research is reported for developing a system of computer programs to aid engineering in the design, fabrication, and testing of large scale integrated circuits, hybrid circuits, and printed circuit boards. The automatic layout programs, analysis programs, and interface programs are discussed.

Kuehlthau, R. L.↗
NASA NTRS2008

Polymer Coats Leads on Implantable Medical Device

Langley Research Center s Soluble Imide (LaRC-SI) was discovered by accident. While researching resins and adhesives for advanced composites for high-speed aircraft, Robert Bryant, a Langley engineer, noticed that one of the polymers he was working with did not behave as predicted. After putting the compound through a two-stage controlled chemical reaction, expecting it to precipitate as a powder after the second stage, he was surprised to see that the compound remained soluble. This novel characteristic ended up making this polymer a very significant finding, eventually leading Bryant and his team to win several NASA technology awards, and an "R&D 100" award. The unique feature of this compound is the way that it lends itself to easy processing. Most polyimides (members of a group of remarkably strong and incredibly heat- and chemical-resistant polymers) require complex curing cycles before they are usable. LaRC-SI remains soluble in its final form, so no further chemical processing is required to produce final materials, like thin films and varnishes. Since producing LaRC-SI does not require complex manufacturing techniques, it has been processed into useful forms for a variety of applications, including mechanical parts, magnetic components, ceramics, adhesives, composites, flexible circuits, multilayer printed circuits, and coatings on fiber optics, wires, and metals. Bryant s team was, at the time, heavily involved with the aircraft polymer project and could not afford to further develop the polymer resin. Believing it was worth further exploration, though, he developed a plan for funding development and submitted it to Langley s chief scientist, who endorsed the experimentation. Bryant then left the high-speed civil transport project to develop LaRC-SI. The result is an extremely tough, lightweight thermoplastic that is not only solvent-resistant, but also has the ability to withstand temperature ranges from cryogenic levels to above 200 C. The thermoplastic s unique characteristics lend it to many commercial applications; uses that Bryant believed would ultimately benefit industry and the Nation. "LaRC-SI," he explains, "is a product created in a government laboratory, funded with money from the tax-paying public. What we discovered helps further the economic competitiveness of the United States, and it was our goal to initiate the technology transfer process to ensure that our work benefited the widest range of people." Several NASA centers, including Langley, have explored methods for using LaRC-SI in a number of applications from radiation shielding and as an adhesive to uses involving replacement of conventional rigid circuit boards. In the commercial realm, LaRC-SI can now be found in several commercial products, including the thin-layer composite unimorph ferroelectric driver and sensor (THUNDER) piezoelectric actuator, another "R&D 100" award winner (Spinoff 2005).

Source record↗
NASA NTRS2010

Inexpensive Implementation of Many Strain Gauges

It has been proposed to develop arrays of strain gauges as arrays of ordinary metal film resistors and associated electronic readout circuitry on printed circuit boards or other suitable substrates. This proposal is a by-product of a development of instrumentation utilizing metal film resistors on printed-circuit boards to measure temperatures at multiple locations. In the course of that development, it was observed that in addition to being sensitive to temperature, the metal film resistors were also sensitive to strains in the printed-circuit boards to which they were attached. Because of the low cost of ordinary metal film resistors (typically <$0.01 apiece at 2007 prices), the proposal could enable inexpensive implementation of arrays of many (e.g., 100 or more) strain gauges, possibly concentrated in small areas. For example, such an array could be designed for use as a computer keyboard with no moving parts, as a device for sensing the shape of an object resting on a surface, or as a device for measuring strains at many points on a mirror, a fuel tank, an airplane wing, or other large object. Ordinarily, the effect of strain on resistance would be regarded as a nuisance in a temperature-measuring application, and the effect of temperature on resistance would be regarded as a nuisance in a strain-measuring application. The strain-induced changes in resistance of the metal film resistors in question are less than those of films in traditional strain gauges. The main novel aspect of present proposal lies in the use of circuitry affording sufficient sensitivity to measure strain plus means for compensating for the effect of temperature. For an array of metal film resistors used as proposed, the readout circuits would include a high-accuracy analog-to-digital converter fed by a low noise current source, amplifier chain, and an analog multiplexer chain. Corrections would be provided by use of high-accuracy calibration resistors and a temperature sensor. By use of such readout circuitry, it would be possible to read the resistances of as many as 100 fixed resistors in a time interval of 1 second at a resolution much greater than 16 bits. The readout data would be processed, along with temperature calibration data, to deduce the strain on the printed-circuit board or other substrate in the areas around the resistors. It should also be possible to also deduce the temperature from the readings.

Berkun, Andrew C.↗
NASA NTRS2008

Making Complex Electrically Conductive Patterns on Cloth

A method for automated fabrication of flexible, electrically conductive patterns on cloth substrates has been demonstrated. Products developed using this method, or related prior methods, are instances of a technology known as 'e-textiles,' in which electrically conductive patterns ar formed in, and on, textiles. For many applications, including high-speed digital circuits, antennas, and radio frequency (RF) circuits, an e-textile method should be capable of providing high surface conductivity, tight tolerances for control of characteristic impedances, and geometrically complex conductive patterns. Unlike prior methods, the present method satisfies all three of these criteria. Typical patterns can include such circuit structures as RF transmission lines, antennas, filters, and other conductive patterns equivalent to those of conventional printed circuits. The present method overcomes the limitations of the prior methods for forming the equivalent of printed circuits on cloth. A typical fabrication process according to the present method involves selecting the appropriate conductive and non-conductive fabric layers to build the e-textile circuit. The present method uses commercially available woven conductive cloth with established surface conductivity specifications. Dielectric constant, loss tangent, and thickness are some of the parameters to be considered for the non-conductive fabric layers. The circuit design of the conductive woven fabric is secured onto a non-conductive fabric layer using sewing, embroidery, and/or adhesive means. The portion of the conductive fabric that is not part of the circuit is next cut from the desired circuit using an automated machine such as a printed-circuit-board milling machine or a laser cutting machine. Fiducials can be used to align the circuit and the cutting machine. Multilayer circuits can be built starting with the inner layer and using conductive thread to make electrical connections between layers.

Chu, Andrew↗