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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5

All sources NASA NTRS DOE OSTI

NASA NTRS1995

Multi-speed multi-phase resolver converter

A multiphase converter circuit generates a plurality of sinusoidal outputs of displaced phase and given speed value from the output of an angular resolver system attachable to a motor excited by these multi-phase outputs, the resolver system having a lower speed value than that of the motor. The angular resolver system provides in parallel format sequential digital numbers indicative of the amount of rotation of the shaft of an angular position sensor associated with the angular resolver system. These numbers are used to excite simultaneously identical addresses of a plurality of addressable memory systems, each memory system having stored therein at sequential addresses sequential values of a sinusoidal wavetrain of a given number of sinusoids. The stored wavetrain values represent sinusoids displaced from each other in phase according to the number of output phases desired. A digital-to-analog converter associated with each memory system converts each accessed word to a corresponding analog value to generate attendant to rotation of the angular resolver a sinusoidal wave of proper phase at each of the plurality of outputs. By properly orienting the angular resolver system with respect to the rotor of the motor, essentially ripple-free torque is supplied to the rotor. The angular resolver system may employ an analog resolver feeding an integrated circuit resolver-to-digital converter to produce the requisite digital values serving as addresses. Alternative versions employing incremental or absolute encoders are also described.

Alhorn, Dean C.↗

NASA NTRS1979

Implementing a bubble memory hierarchy system

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Segura, R.↗

NASA NTRS1990

Programming distributed memory architectures using Kali

Programming nonshared memory systems is more difficult than programming shared memory systems, in part because of the relatively low level of current programming environments for such machines. A new programming environment is presented, Kali, which provides a global name space and allows direct access to remote data values. In order to retain efficiency, Kali provides a system on annotations, allowing the user to control those aspects of the program critical to performance, such as data distribution and load balancing. The primitives and constructs provided by the language is described, and some of the issues raised in translating a Kali program for execution on distributed memory systems are also discussed.

Mehrotra, Piyush↗

NASA NTRS2006

Development and Testing of an Axial Halbach Magnetic Bearing

The NASA Glenn Research Center has developed and tested a revolutionary Axial Halbach Magnetic Bearing. The objective of this work is to develop a viable non-contact magnetic thrust bearing utilizing Halbach arrays for all-electric flight, and many other applications. This concept will help to reduce harmful emissions, reduce the Nation s dependence on fossil fuels and mitigate many of the concerns and limitations encountered in conventional axial bearings such as bearing wear, leaks, seals and friction loss. The Axial Halbach Magnetic Bearing is inherently stable and requires no active feedback control system or superconductivity as required in many magnetic bearing designs. The Axial Halbach Magnetic Bearing is useful for very high speed applications including turbines, instrumentation, medical systems, computer memory systems, and space power systems such as flywheels. Magnetic fields suspend and support a rotor assembly within a stator. Advanced technologies developed for particle accelerators, and currently under development for maglev trains and rocket launchers, served as the basis for this application. Experimental hardware was successfully designed and developed to validate the basic principles and analyses. The report concludes that the implementation of Axial Halbach Magnetic Bearings can provide significant improvements in rotational system performance and reliability.

Eichenberg, Dennis J.↗

NASA NTRS1991

High density packaging and interconnect of massively parallel image processors

This paper presents conceptual designs for high density packaging of parallel processing systems. The systems fall into two categories: global memory systems where many processors are packaged into a stack, and distributed memory systems where a single processor and many memory chips are packaged into a stack. Thermal behavior and performance are discussed.

Carson, John C.↗

NASA NTRS1987

Approximate Feedback Control for a System With Memory

Report presents algorithm for calculating feedback gain for control of hereditary dynamical systems with control delay. Problem is to approximate optimal feedback gain that minimizes cost function of state and control. Theory applicable to design of controllers for mechanical systems subject to thermal deformation, electrical systems with delay, electrical systems with plasma components, and other systems that exhibit memory.

Milman, Mark H.↗

NASA NTRS2006

Programs for Testing Processor-in-Memory Computing Systems

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.]

Katz, Daniel S.↗

NASA NTRS1990

Ray tracing on distributed memory parallel systems

Among the many techniques in computer graphics, ray tracing is prized because it can render realistic images, albeit at great computational expense. In this note, the performance of several approaches to ray tracing on a distributed memory parallel system is evaluated. A set of performance instrumentation tools and their associated visualization software are used to identify the underlying causes of performance differences.

Jensen, David W.↗

NASA NTRS1990

Supporting shared data structures on distributed memory architectures

Programming nonshared memory systems is more difficult than programming shared memory systems, since there is no support for shared data structures. Current programming languages for distributed memory architectures force the user to decompose all data structures into separate pieces, with each piece owned by one of the processors in the machine, and with all communication explicitly specified by low-level message-passing primitives. A new programming environment is presented for distributed memory architectures, providing a global name space and allowing direct access to remote parts of data values. The analysis and program transformations required to implement this environment are described, and the efficiency of the resulting code on the NCUBE/7 and IPSC/2 hypercubes are described.

Koelbel, Charles↗

DOE OSTI2021

Design Space Exploration of Emerging Memory Technologies for Machine Learning Applications

Memory design space exploration methods study memory systems’ performances and limitations before implementation. The computer memory design space has grown exponentially because of the enormous growth of memory types, memory controllers, and application software. Computer simulators are commonly used for memory design space exploration. However, complex memory simulations take an enormous amount of time. Hence, in this paper, we proposed a machine learning-based design space exploration method for dynamic random-access memory and non-volatile memory systems. We applied our method to the CosmoGAN and LeNet applications to predict the following six memory response parameters: (i) bandwidth, (ii) power, (iii) average latency, (iv) average total latency, (v) memory reads, and (vi) memory writes. Our experimental results show that machine learning models can predict memory response parameter values faster than simulations. We used support vector machine, random forest, and gradient boosting machine learning models. We observed that the support vector machine provides better performance for bandwidth, average latency, and average total latency. The random forest model works better for memory reads and writes. The gradient boosting model provides superior prediction performance for power. We provide a detailed discussion on learning curve characteristics, error analysis, and memory type recommendation.

Hasan, S M Shamimul↗

NASA NTRS2008

High-Density, High-Bandwidth, Multilevel Holographic Memory

A proposed holographic memory system would be capable of storing data at unprecedentedly high density, and its data transfer performance in both reading and writing would be characterized by exceptionally high bandwidth. The capabilities of the proposed system would greatly exceed even those of a state-of-the art memory system, based on binary holograms (in which each pixel value represents 0 or 1), that can hold .1 terabyte of data and can support a reading or writing rate as high as 1 Gb/s. The storage capacity of the state-of-theart system cannot be increased without also increasing the volume and mass of the system. However, in principle, the storage capacity could be increased greatly, without significantly increasing the volume and mass, if multilevel holograms were used instead of binary holograms. For example, a 3-bit (8-level) hologram could store 8 terabytes, or an 8-bit (256-level) hologram could store 256 terabytes, in a system having little or no more size and mass than does the state-of-the-art 1-terabyte binary holographic memory. The proposed system would utilize multilevel holograms. The system would include lasers, imaging lenses and other beam-forming optics, a block photorefractive crystal wherein the holograms would be formed, and two multilevel spatial light modulators in the form of commercially available deformable-mirror-device spatial light modulators (DMDSLMs) made for use in high speed input conversion of data up to 12 bits. For readout, the system would also include two arrays of complementary metal oxide/semiconductor (CMOS) photodetectors matching the spatial light modulators. The system would further include a reference-beam sterring device (equivalent of a scanning mirror), containing no sliding parts, that could be either a liquid-crystal phased-array device or a microscopic mirror actuated by a high-speed microelectromechanical system. Time-multiplexing and the multilevel nature of the DMDSLM would be exploited to enable writing and reading of multilevel holograms. The DMDSLM would also enable transfer of data at a rate of 7.6 Gb/s or perhaps somewhat higher.

Chao, Tien-Hsin↗

NASA NTRS1973

Design, fabrication, testing and delivery of a feasibility model laminated ferrite memory

The effect of using multiword addressing with laminated ferrite arrays was made. Both a reduction in the number of components, and a reduction in power consumption was obtained for memory capacities between one million bits and one million words. An investigation into the effect of variations in the processing steps resulted in a number of process modifications that improved the quality of the arrays. A feasibility model laminated ferrite memory system was constructed by modifying a commercial plated wire memory system to operate with laminated ferrite arrays. To provide flexibility for the testing of the laminated ferrite memory, an exerciser has been constructed to automatically control the loading and recirculation of arbitrary size checkerboard patterns of one's and zero's and to display the patterns of stored information on a CRT screen.

Heckler, H. C.↗

NASA NTRS1993

Multiple-User, Multitasking, Virtual-Memory Computer System

Computer system designed and programmed to serve multiple users in research laboratory. Provides for computer control and monitoring of laboratory instruments, acquisition and anlaysis of data from those instruments, and interaction with users via remote terminals. System provides fast access to shared central processing units and associated large (from megabytes to gigabytes) memories. Underlying concept of system also applicable to monitoring and control of industrial processes.

Generazio, Edward R.↗

DOE OSTI2021

Flexible optimized data handling in systems with multiple memories

Methods and systems for optimizing an application for a computing system having multiple distinct memory locations that are interconnected by one or more communication channels include determining one or more data handling properties for a data region in an application. One or more data handling policies for the data region are determined based on the one or more data handling properties. Data setup costs are determined for a scope in the application that uses the data region in different memory locations based on the one or more data handling properties. The application is optimized in accordance with the one or more data handling policies and the data setup costs for the different memory locations.

Chen, Tong↗

DOE OSTI2023

Flexible optimized data handling in systems with multiple memories

Chen, Tong↗

NASA NTRS1972

An adaptive replacement algorithm for paged-memory computer systems.

A general class of adaptive replacement schemes for use in paged memories is developed. One such algorithm, called SIM, is simulated using a probability model that generates memory traces, and the results of the simulation of this adaptive scheme are compared with those obtained using the best nonlookahead algorithms. A technique for implementing this type of adaptive replacement algorithm with state of the art digital hardware is also presented.

Thorington, J. M., Jr.↗

NASA NTRS1999

MLP: A Parallel Programming Alternative to MPI for New Shared Memory Parallel Systems

Recent developments at the NASA AMES Research Center's NAS Division have demonstrated that the new generation of NUMA based Symmetric Multi-Processing systems (SMPs), such as the Silicon Graphics Origin 2000, can successfully execute legacy vector oriented CFD production codes at sustained rates far exceeding processing rates possible on dedicated 16 CPU Cray C90 systems. This high level of performance is achieved via shared memory based Multi-Level Parallelism (MLP). This programming approach, developed at NAS and outlined below, is distinct from the message passing paradigm of MPI. It offers parallelism at both the fine and coarse grained level, with communication latencies that are approximately 50-100 times lower than typical MPI implementations on the same platform. Such latency reductions offer the promise of performance scaling to very large CPU counts. The method draws on, but is also distinct from, the newly defined OpenMP specification, which uses compiler directives to support a limited subset of multi-level parallel operations. The NAS MLP method is general, and applicable to a large class of NASA CFD codes.

Taft, James R.↗

NASA NTRS1996

Man-Machine Interaction Design and Analysis System (MIDAS): Memory Representation and Procedural Implications for Airborne Communication Modalities

The Man-Machine Interaction Design and Analysis System (MIDAS) has been under development for the past ten years through a joint US Army and NASA cooperative agreement. MIDAS represents multiple human operators and selected perceptual, cognitive, and physical functions of those operators as they interact with simulated systems. MIDAS has been used as an integrated predictive framework for the investigation of human/machine systems, particularly in situations with high demands on the operators. Specific examples include: nuclear power plant crew simulation, military helicopter flight crew response, and police force emergency dispatch. In recent applications to airborne systems development, MIDAS has demonstrated an ability to predict flight crew decision-making and procedural behavior when interacting with automated flight management systems and Air Traffic Control. In this paper we describe two enhancements to MIDAS. The first involves the addition of working memory in the form of an articulatory buffer for verbal communication protocols and a visuo-spatial buffer for communications via digital datalink. The second enhancement is a representation of multiple operators working as a team. This enhanced model was used to predict the performance of human flight crews and their level of compliance with commercial aviation communication procedures. We show how the data produced by MIDAS compares with flight crew performance data from full mission simulations. Finally, we discuss the use of these features to study communications issues connected with aircraft-based separation assurance.

Corker, Kevin M.↗