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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Data-driven based coordinated smart inverter control for distributed energy resources

Smart inverters (SI) for distributed energy resources (DER) are becoming popular since they have the ability to stabilize as well as restore the voltage and frequency of power systems. Aiming at establishing the mathematical models combined with SI control methods, multiple optimization methods are developed. However, the computational complexity of solving such a mathematical model with various uncertainties limits the real-time application of the SI control. To conquer this challenge, a data-driven-based SI control approach is developed to achieve coordinated control in the high penetration DER system. First, an optimization problem for maximizing the active power generation and minimizing the power loss is designed using the Volt/VAR control. To reduce the time consumption, the recurrent neural network (RNN) is proposed to model the relationship between the uncertainties and control actions during the offline site. The RNN with different sub-structures such as the long short-term memory cell and gated recurrent unit cell are included to enrich the diversity of features. In the last stage, different experiment comparisons, including multiple uncertainties maps and stateof- art machine learning methods, are conducted to verify the effectiveness of the proposed method based on the IEEE 123 bus power system. The results demonstrate that the proposed method can effectively achieve a rapid and coordinated control with a lower error rate.

Qiu, Wei↗
DOE OSTI2023

A new class of antibodies that overcomes a steric barrier to cross-group neutralization of influenza viruses

Antibody titers that inhibit the influenza virus hemagglutinin (HA) from engaging its receptor are the accepted correlate of protection from infection. Many potent antibodies with broad, intra-subtype specificity bind HA at the receptor binding site (RBS). One barrier to broad H1-H3 cross-subtype neutralization is an insertion (133a) between positions 133 and 134 on the rim of the H1 HA RBS. We describe here a class of antibodies that overcomes this barrier. These genetically unrestricted antibodies are abundant in the human B cell memory compartment. Analysis of the affinities of selected members of this class for historical H1 and H3 isolates suggest that they were elicited by H3 exposure and broadened or diverted by later exposure(s) to H1 HA. RBS mutations in egg-adapted vaccine strains cause the new H1 specificity of these antibodies to depend on the egg adaptation. The results suggest that suitable immunogens might elicit 133a-independent, H1-H3 cross neutralization by RBS-directed antibodies.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2024

The Single Event Error (SEE) test and analysis of the CMS Endcap Timing Layer readout chip

The ETROC2, the first full size and full functionality prototype chip for the CMS Endcap Timing Layer readout, is strategically designed to meet the SEE immunity requirements of detector operation with the low power constraint. The triplicated periphery and pixel I2C configuration registers are designed with self-correction feature. The pixel readout control is centralized in the global readout and fully triplicated. The pixel readout is not triplicated, instead protected with power-efficient one-bit correction Hamming code. The TMR protection of the on-pixel threshold calibration can be turned off allowing the detection of the beam spot during the beam test by checking the bit-flips of the internal memory cells. In the initial proton beam test in January 2024, the chip readout process did not hang throughout the tests. The Hamming code correction strategy works because the error corrected TDC data were observed in the data frames. The error-injection simulation is performed to analy ze the small number of bit-flips in the configuration registers. We also performed SEE testing with a heavy ion beam in April and the data analysis is ongoing. The detailed design on the SEE immunity and the testing as well as simulation results will be presented, including follow-up SEE testing results in May and June 2024.

Gong, Datao↗
NASA NTRS1971

Fault tolerant sequential machines

Memory cell fault tolerant sequential machine synthesis, considering masking feasibility and lower bounds on minimum redundancy

Meyer, J. F.↗
NASA NTRS1978

Annual Conference on Nuclear and Space Radiation Effects, 15th, University of New Mexico, Albuquerque, N. Mex., July 18-21, 1978, Proceedings

Radiation effects in MOS devices and circuits are considered along with radiation effects in materials, space radiation effects and spacecraft charging, SGEMP, IEMP, EMP, fabrication of radiation-hardened devices, radiation effects in bipolar devices and circuits, simulation, energy deposition, and dosimetry. Attention is given to the rapid anneal of radiation-induced silicon-sapphire interface charge trapping, cosmic ray induced errors in MOS memory cells, a simple model for predicting radiation effects in MOS devices, the response of MNOS capacitors to ionizing radiation at 80 K, trapping effects in irradiated and avalanche-injected MOS capacitors, inelastic interactions of electrons with polystyrene, the photoelectron spectral yields generated by monochromatic soft X radiation, and electron transport in reactor materials.

Simons, M.↗
NASA NTRS1985

On the factorization of block-tridiagonals without storage constraints

In many programs solving difference equations, problem size is restricted by the number of available memory cells. A strategy has been developed to permit trade-offs between the number of floating point operations required and storage requirements for the solution of certain problems such as block tridiagonal systems of equations. This is done by recomputing some intermediate results instead of storing them. Reducing the storage to the square root of the current requirement will roughly double the number of computations. In theory, if m is the order of each sub-matrix in the block tridiagonal matrix, one can solve any linear system with only 5 sq m + 1 temporary storage cells. This method lends itself to efficient use on computers with parallel processing or vector processing architectures. On these computers the larger number of floating point operations is more than offset by the decrease in I/O and the increased percentage of vector operations made possible by this algorithm.

Merriam, M. L.↗
NASA NTRS1988

Blanket Gate Would Address Blocks Of Memory

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Lambe, John↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1988

An exact, closed-form expression of the integral chord-length distribution for the calculation of single-event upsets induced by cosmic rays

This paper presents a derivation of an exact closed-form expression of the integral chord-length distribution for the calculation of single-event upsets (SEUs) in an electronic memory cell, caused by cosmic rays. Results computed for two rectangular parallelepipeds using this exact expression are compared with those computed with Bradford's (1979) semiexact expression of C(x). It is found that the values of C(x) are identical for x equal or smaller than b but are vastly different for x greater than b. Moreover, while C(x) of Bradford gives reasonably accurate values of SEU rate for certain sets of computational parameters, it gives values more than 10 times larger than the correct values for other sets of parameters.

Luke, Keung L.↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
NASA NTRS1991

Fast Magnetoresistive Random-Access Memory

Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

Wu, Jiin-Chuan↗
NASA NTRS1991

Magnetic Analog Random-Access Memory

Proposed integrated, solid-state, analog random-access memory base on principle of magnetic writing and magnetoresistive reading. Current in writing conductor magnetizes storage layer. Remanent magnetization in storage layer penetrates readout layer and detected by magnetoresistive effect or Hall effect. Memory cells are part of integrated circuit including associated reading and writing transistors. Intended to provide high storage density and rapid access, nonvolatile, consumes little power, and relatively invulnerable to ionizing radiation.

Katti, Romney R.↗
NASA NTRS1990

Alpha-particle sensitive test SRAMs

A bench-level test is being developed to evaluate memory-cell upsets in a test SRAM designed with a cell offset voltage. This offset voltage controls the critical charge needed to upset the cell. The effect is demonstrated using a specially designed 2-micron n-well CMOS 4-kb test SRAM and a Po-208 5.1-MeV 0.61-LET alpha-particle source. This test SRAM has been made sensitive to alpha particles through the use of a cell offset voltage, and this has allowed a bench-level characterization in a laboratory setting. The experimental data are linked to a alpha-particle interaction physics and to SPICE circuit simulations through the alpha-particle collection depth. The collection depth is determined by two methods and found to be about 7 micron. In addition, alpha particles that struck outside the bloated drain were able to flip the SRAM cells. This lateral charge collection was observed to be more than 6 micron.

Buehler, M. G.↗
NASA NTRS1991

An area model for on-chip memories and its application

An area model suitable for comparing data buffers of different organizations and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage. The model gave less than 10 percent error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches, direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas, both direct-mapped and set-associative caches perform better than fully associative caches.

Mulder, Johannes M.↗
NASA NTRS1991

A RAM architecture for concurrent access and on-chip testing

A novel RAM architecture supporting concurrent memory access and on-chip testing (CMAT) is proposed. A large-capacity memory chip is decomposed into test neighborhoods (TNDs), each of which is tested independently. When there are data stored in a TND, the data are saved into a buffer before testing the TND, and the TND's contents are restored using buffered data after testing the TND. If an external request is not made to the TND, the request can be directed to the addressed memory cells. Otherwise, the buffered data can be loaded back into the TND, or the request is detoured to a corresponding buffer. By deriving an analytical model, the performance penalty and hardware overhead of the CMAT architecture are shown to be very small.

Liu, Jyh-Charn↗
NASA NTRS1993

Rapid, Nondestructive Readout From Ferroelectric Memory

Proposed devices with nondestructive readout offer attractive alternatives for rugged, solid-state memories suitable for contactless optical addressing and parallel processing and for nonvolatile analog memories. Pulses of light from lasers induce photoresponses in ferroelectric capacitors. Magnitude and polarity of response of each capacitor indicates magnitude and polarity of remanent polarization which, in turn, represents datum stored in that memory cell.

Thakoor, Sarita↗
NASA NTRS1995

Gas-Sensing Flip-Flop Circuits

Gas-sensing integrated circuits consisting largely of modified static random-access memories (SRAMs) undergoing development, building on experience gained in use of modified SRAMs as radiation sensors. Each SRAM memory cell includes flip-flop circuit; sensors exploit metastable state that lies between two stable states (corresponding to binary logic states) of flip-flop circuit. Voltages of metastable states vary with exposures of gas-sensitive resistors.

Buehler, Martin G.↗
NASA NTRS1994

FFT Computation with Systolic Arrays, A New Architecture

The use of the Cooley-Tukey algorithm for computing the l-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started.

Boriakoff, Valentin↗