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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

A Multi-Metrics In Situ Aging Detector for SiC Power MOSFET Modules with Full Driver-Integration Capability

In this paper, the concept and prototype of an aging detector for silicon carbide (SiC) power metal oxide semiconductor field effect transistor (MOSFET) are proposed and described. It leverages the resonant peak values of gate-source voltage at different instants during the switching transients to decode the change of multiple aging indicators, such as the increases of on-state resistance and threshold voltage. Modeling-based analysis is conducted to support the idea. The detector can be fully integrated into gate drivers without any additional connection to the power stage and is functional during normal power stage operation. A prototype unit was built, and preliminary tests were conducted to validate the idea and the practicality of the detector.

aging↗
DOE OSTI2022

Probing the Atomic Scale Mechanisms of Time Dependent Dielectric Breakdown in Si/SiO 2 MOSFETs (June 2022)

Here we report on an atomic-scale study of trap generation in the initial/intermediate stages of time-dependent dielectric breakdown (TDDB) in high-field stressed (100) Si/SiO2 MOSFETs using two powerful analytical techniques: electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR). We find the dominant EDMR-sensitive traps generated throughout the majority of the TDDB process to be silicon dangling bonds at the (100) Si/SiO2 interface (Pb0 and Pb1 centers) for both the spin-dependent recombination (SDR) and trap-assisted tunneling (SDTAT) processes. We find this generation to be linked to both changes in the calculated interface state densities as well as changes in the NZFMR spectra for recombination events at the interface, indicating a redistribution of mobile magnetic nuclei which we conclude could only be due to the redistribution of hydrogen at the interface. Additionally, we observe the generation of traps known as E’ centers in EDMR measurements at lower experimental temperatures via SDR measurements at the interface. Our work strongly suggests the involvement of a rate-limiting step in the tunneling process between the silicon dangling bonds generated at the interface and the ones generated throughout the oxide.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Design Considerations for High-Voltage Insulated Gate Drive Power Supply for 10-kV SiC MOSFET Applied in Medium-Voltage Converter

High-performance gate drive power supply (GDPS) plays a crucial role in ensuring the reliability and safety of the gate driver for power semiconductor devices. This article focuses on the design of a high-voltage-insulated GDPS for the 10-kV silicon carbide MOSFET in medium-voltage (MV) application. Design considerations, including insulation scheme, high-voltage-insulated transformer design, and load voltage regulation scheme, are proposed. In addition, the performance of the secondary-side-regulated (SSR) GDPS and that of the primary-side-regulated (PSR) GDPS are compared for several aspects, including interwinding capacitance, load voltage regulation rate, conversion efficiency, and hardware complexity. Finally, an SSR GDPS and a PSR GDPS, with an insulation voltage of 20 kV, are built in the lab. Furthermore, the test results demonstrate that the PSR GDPS is more preferable because of lower interwinding capacitance, lower load voltage regulation rate, higher conversion efficiency, and simpler control circuit.

42 ENGINEERING↗
DOE OSTI2026

TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET

We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.

COTS↗
DOE OSTI2021

Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade- Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. Here, the static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200oC. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.

4H-SiC↗
NASA NTRS1997

Investigations into the Power MOSFET SEGR Phenomenon and its Physical Mechanism

The state of understanding of the destructive SEGR event in power MOSFETs is relatively mature with large published efforts, both experimental and theoretical. However, gasps remain in the uderstanding of the phenomenon, including unexplained anomalies, emperical-only dependencies on some important device and incident ion physical parameters, and limited insight into latent effets.

MOSFET SEGR↗
NASA NTRS2008

Current Leakage Evolution in Partially Gate Raptured Power MOSFETs

It has been observed that power MOSFETs can experience an SEGR and continue to function with altered parameters. We propose that there are three different types of SEGR modes; the micro-break, the thermal runaway, and the avalanche breakdown. Data that demonstrates these stages of device failure are presented as well as a proposed model for the micro-break. Brief discussions of the other modes, based on analysis combined with our interpretations of the older literature, are also given.

metal oxide semiconductor field-effect transistors↗
NASA NTRS2017

Radiation Hardness Study on SiC Power MOSFETs

As an emerging technology, silicon carbide (SiC) power MOSFETs are showing great potential for higher temperature/power rating, higher efficiency, and reduction in size and weight, which makes this technology ideal for high temperature, harsh environment applications such as downhole, medical, avionic, or even space applications. Radiation tolerance therefore becomes a critical aspect of the device performance in such environments. In this work, we explored radiation hardness of SiC devices to total ionizing dose (TID), neutron-induced single-event burnout (SEB), and heavy-ion induced single-event effects (SEE).

SiC↗
NASA NTRSDate not supplied

Design and Testing of a Hard-Fault Protection Circuit for a 1 kV SiC MOSFET Inverter

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to prevent exceeding the current rating of these devices during low-inductance fault events. This paper explores the use of an air core Rogowski coil topology to mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-to-phase fault in under one microsecond, tested up to DC link voltages of 1 kV. This paper details the theory, design, simulation, and successful test results of this method.

hard fault protection↗
NASA NTRS2010

NASA Engineering and Safety Center Technical Bulletin No. 10-01: Power MOSFET Thermal Instability

In the quest for faster switching times and lower “on resistance” the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), produced since 1998, has achieved most intended goals. Unfortunately, lower “on resistance” and higher switching speeds in the designs now being produced allow the charge carrier dominated region to develop conditions that could lead to thermal runaway. Temperatures above 450º C on any location within the part can cause the metals to begin migrating causing a fatal short circuit.

Metal-Oxide Semiconductor Field-Effect Transistor ↗
NASA NTRS2024

Single Event Effects Test Report IXYS IXTA96P085T P-Channel -85V MOSFET

This study was undertaken to determine the destructive single event effect and degradation susceptibility of the IXTA96P085T P-Channel -85V MOSFET from IXYS. The device was monitored for destructive single event effects and degradation during exposure to a heavy ion beam at the Berkeley Accelerator Space Effects (BASE) Facility at the Lawrence Berkeley National Laboratory (LBNL). Gate and drain currents were measured during irradiation and a basic set of electrical characterizations was performed following each fluence exposure to assess heavy ion induced damage. The test date was April 10, 2024. This characterization is application specific.

MOSFET↗
NASA NTRS2024

Single Event Effects Test Report Vishay Siliconix Si7113DN P-Channel 100V MOSFET

This study was undertaken to determine the destructive single event effect and degradation susceptibility of the Si7113DN P-Channel 100V MOSFET from Vishay Siliconix. The device was monitored for destructive single event effects and degradation during exposure to a heavy ion beam at the Berkely Accelerator Space Effects (BASE) Facility at the Lawrence Berkely National Laboratory (LBNL).

MOSFET↗
NASA NTRSDate not supplied

Design and Development of a Fluid Immersion Cooled, SiC MOSFET, 37.5 kW, Bi-Directional Motor Converter

NASA's SUb-sonic Single Aft eNgine (SUSAN) aircraft is a concept aircraft whose architecture is that of a subsonic regional jet transport aircraft. SUSAN contains a single turbofan engine coupled to an electrified aircraft propulsion (EAP) system. To provide a path towards this goal, a 25% scale version of the SUSAN aircraft is being researched. A main component of the 25% power train is the Motor And Generator Intelligent Converter (MAGIC). This paper presents the design, development, and initial test results from MAGIC, a 37.5 kW, fluid immersion cooled, silicon carbide (SiC) MOSFET-based, bi-directional converter and controller.

PAO↗
NASA NTRSDate not supplied

Design and Development of a Fluid Immersion Cooled, SiC MOSFET, 37.5 kW, Bi-Directional Motor Converter

NASA's SUb-sonic Single Aft eNgine (SUSAN) aircraft is a concept aircraft whose architecture is that of a subsonic regional jet transport aircraft. SUSAN contains a single turbofan engine coupled to an electrified aircraft propulsion (EAP) system. To provide a path towards this goal, a 25% scale version of the SUSAN aircraft is being researched. A main component of the 25% power train is the Motor And Generator Intelligent Converter (MAGIC). This paper presents the design, development, and initial test results from MAGIC, a 37.5 kW, fluid immersion cooled, silicon carbide (SiC) MOSFET-based, bi-directional converter and controller.

Immersion↗
DOE OSTI2020

Hardware Design and Demonstration of a 100kW, 99% Efficiency Dual Active Half Bridge Converter Based on 1700V SiC Power MOSFET

High efficiency, high density and galvanically isolated power converters are attractive for numerous medium voltage high power applications. This paper presents a 1.5kVdc, 100kW bidirectional Dual Active Half Bridge (DAHB) using newly developed 1.7kV SiC MOSFET modules. The DAHB achieved an efficiency of 98.6% at full load of 100kW and a maximum of 99% at 45kW, operating as an isolated DC/DC converter. The converter also achieved an efficiency of 97.8% operating as an isolated DC/AC inverter. An optimized PCB-based busbar design has significantly reduced the voltage overshoot across the device, making the design suitable for 1500Vdc input application such as 1500V PV inverters. Typical partial discharge inception voltage (PDIV) of the optimized PCB busbar is 1.7kVpeak with total charge <10pC. The power density of the DAHB converter is 1.8MVA/m 3 which is much higher than traditional two-stage industry products. The DAHB converter can be used as a building block for a 4.16kV/1MVA utility scale PV systems with input parallel and output series configuration.

Xu, Wei↗
DOE OSTI2023

Design and Demonstration of an 850 V dc to 13.8 kV ac 100 kW Three-phase Four-wire Power Conditioning System Converter Using 10 kV SiC MOSFETs

In this paper, an 850 V dc to 13.8 kV ac 100 kW modular multilevel three-phase four-wire dc/ac converter based on 10 kV SiC MOSFETs is designed and demonstrated. The design considerations of key components, including the dc-link, device cooling, gate driver, isolated gate driver power supply (GDPS), medium voltage (MV) ac filter inductor, MV and medium frequency transformer, and the mechanical design are discussed. Two converters are designed, and two prototypes are developed, to study the converter paralleling operation and scalability. Both converters are fully tested up to their voltage and power ratings. However, the two converters are not identical. Based on the design and test results of the first converter, the MV power stage, transformer design, GDPS, as well as the low voltage power stage in the second converter are improved for smaller size and/or higher efficiency. Compared to the version 1 converter, the version 2 converter achieves 49% volume reduction and 2 percentage point efficiency improvement, with a peak efficiency of 98.4% at the rated power.

Li, Haiguo↗