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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Circular queue management with split indexes

Methods and apparatus for managing circular queues are disclosed. A pointer designates an index position of a particular queue element and contains an additional pointer state, whereby two pointer values (split indexes) can designate the same index position. Front and rear pointers are respectively managed by dequeue and enqueue logic. The front pointer state and rear pointer state distinguish full and empty queue states when both pointers designate the same index position. Asynchronous dequeue and enqueue operations are supported, no lock is required, and no queue entry is wasted. Hardware and software embodiments for numerous applications are disclosed.

Miniskar, Narasinga Rao↗
DOE OSTI2023

Evaluation of the first version of the new RFPI system dedicated to PIP-II project accelerator

The Low-Level Radio Frequency (LLRF) control system is one of the most critical superconducting linac infrastructures responsible for the parameters of the beam acceleration. The LLRF system mainly focuses on the electromagnetic field parameters inside the cavity. While it incorporates fast feedback algorithms to optimize energy transfer to the passing particle beam it does not follow other cryomodule or cavity parameter changes. The Radio Frequency Protection Interlock (RFPI) system closely monitors various factors (like cryomodule vacuum, beamline vacuum, field emission probe current level, temperature, RF signal leakage, etc). Its simple but reliable logic has to provide an instant decision about the LLRF system or high-power amplifier output signal blocking in case of safety region excitation. This contribution presents a new version of the RFPI system which logic is implemented in the FPGA chip. The initial work on the prototype of the new system design resulted in the PoC (Proof of Concept) device. The PoC offers the possibility of various protection logic configurations, input signals parameters evaluation, and modularity aspects verification. The structure and test results from the device evaluation are summarized and discussed in this contribution.

43 PARTICLE ACCELERATORS↗
DOE OSTI2025

Redefining Design for Remanufacturing: A Practical Methodology for Prioritizing Remanufacturing Design Rules

Products are often discarded when they fail or no longer meet user needs. These outcomes are frequently shaped by early design decisions. While remanufacturing offers a sustainable alternative by restoring products to like‐new condition, its potential is often limited by designs that do not consider remanufacturing from the outset. This research addresses that challenge by introducing a structured Design for Remanufacturing (DfRem) methodology and a CAD‐integrated tool to support real‐time design decisions. The DfRem framework introduces a new primary design function focused on preserving product functionality across its life cycle. It is supported by a fault tree that identifies failure modes that limit remanufacturing potential and a hierarchy of design principles including Prevent, Minimize, Relocate, Restore, and others. Each principle is linked to actionable design rules that help engineers reduce the need for remanufacturing or improve its efficiency when necessary. To operationalize this framework, we developed CAD plugins for Autodesk Inventor and PTC Creo. These tools use a state machine model to present prioritized design rules based on selected failure modes and user input. By embedding DfRem logic directly into widely used CAD environments, the tool enables engineers to make sustainability‐informed decisions without disrupting existing workflows. Furthermore, this approach highlights the critical role of design in enabling circular and resource‐efficient product development, making remanufacturing a more practical and accessible strategy during the early stages of product design.

CAD↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗
DOE OSTI2022

A multi-stage single photochrome system for controlled photoswitching responses

The ability of molecular photoswitches to convert on/off responses into large macroscale property change is fundamental to light-responsive materials. However, moving beyond simple binary responses necessitates the introduction of new elements that control the chemistry of the photoswitching process at the molecular scale. To achieve this goal, we designed, synthesized and developed a single photochrome, based on a modified donor–acceptor Stenhouse adduct (DASA), capable of independently addressing multiple molecular states. The multi-stage photoswitch enables complex switching phenomena. To demonstrate this, we show spatial control of the transformation of a three-stage photoswitch by tuning the population of intermediates along the multi-step reaction pathway of the DASAs without interfering with either the first or final stage. This allows for a photonic three-stage logic gate where the secondary wavelength solely negates the input of the primary wavelength. Finally, these results provide a new strategy to move beyond traditional on/off binary photochromic systems and enable the design of future molecular logic systems.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2020

Logic in Memory Emulator

Logic in Memory Emulator (LiME) is a hardware/software tool specially designed for memory system evaluation and experiment. Emerging memories display a wide range of bandwidths, latencies, and capacities, making it challenging for the computer architect to navigate the design space of potential memory configurations, and for the application developer to assess performance implications of using such memories. With the LiME framework, architectural ideas can be prototyped in great detail yet with sufficient performance to support realistic evaluation on long running applications. LiME consists of two fundamental components: 1) the hardware and OS infrastructure for the emulator, and 2) a suite of benchmark applications to assist in characterizing the performance of current and future computer architectures. Some of the applications have been collected from other open source projects. Uses: Logging, replay and analysis of an application's memory behavior Evaluate impact of emerging memory technology on application performance. Emulate complex memory interactions in whole applications orders of magnitude faster than software simulation. Emulate acceleration hardware co-located with the memory subsystem. Features: Capture and log external memory accesses to a separate off-chip memory device without affecting application execution. Memory traces include the address, length, timestamp, and optionally the data for each transaction. Captured trace data can be saved to an SD card for off-line analysis. Configure a wide range of memory latencies in sub-nanosecond increments that encompass highbandwidth and storage class memories. Specify regions of interest (ROI) in applications to reduce the amount of trace data captured for analysis. Currently supports execution on Xilinx Zynq SoC which integrates an ARM processor with FPGA logic on a single device. Applications can be run under Linux or in bare metal mode on the ARM cores.

Jain, AbhishekK↗
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗
DOE OSTI2024

Recent advancements in chiral spintronics: from molecular-level insights to device applications. A prospect based on the interplay between physical and chemical properties of chiral systems

This review discusses recent advancements in chiral-based spin-electronic devices achieved using suitable combinations of organic, inorganic and hybrid materials. The focus is on how chirality can be effectively used to control spin in practical applications, particularly in spintronic sensors and consumer devices. Interestingly, the underlying mechanism for this control is the chiral-induced spin selectivity (CISS) effect, which links the structural chirality of a material to its spin-selective electronic transport properties. The CISS effect arises from the observation that charge transmission in chiral systems is spin selective. Experimental evidence suggests a relationship between electron spin and the structural handedness of the material. In conclusion, this unique structure-transport relationship can be exploited to design a wide range of spintronics devices, including memory, transistors, logic gates and molecular q-bits.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Spin injection by spin–charge coupling in proximity induced magnetic graphene

Abstract Within the field of spintronics major efforts are directed towards developing applications for spin-based transport devices made fully out of two-dimensional materials. In this work we present an experimental realization of a spin-valve device where the generation of the spin signal is exclusively attributed to the spin-dependent conductivity of the magnetic graphene resulting from the proximity of an interlayer antiferromagnet, chromium sulfide bromide (CrSBr). We clearly demonstrate that the usage of the conventional air-sensitive 3D magnetic contacts can be fully avoided when graphene/CrSBr heterostructures are employed. Moreover, apart from providing exceptionally long spin relaxation length, the usage of graphene for both generation and transport of the spin allows to automatically avoid the conductivity mismatch between the source and the channel circuits that has to be considered when using conventional low-resistive contacts. Our results address a necessary step in the engineering of spintronic circuitry out of layered materials and precede further developments in the area of complex spin-logic devices. Moreover, we introduce a fabrication procedure where we designed and implemented a recipe for the preparation of electrodes via a damage-free technique that offers an immediate advantage in the fields of air-sensitive and delicate organic materials.

36 MATERIALS SCIENCE↗
DOE OSTI2023

A Schottky Tune Meter for the Fermilab Mu2E Delivery Ring

The Mu2E experiment will measure the ratio of the rate of the neutrinoless, coherent conversion of muons into electrons as a measure of Charged Lepton Flavor Violation. As part of the Mu2E experiment, a proton storage ring, called the Delivery Ring, will utilize resonant extraction to slow-spill protons to the experiment. To regulate and optimize the Delivery Ring resonant extraction process, a fast tune measurement scheme will be required. This Mu2E tune meter will measure the average tune and the tune spectrum, in multiple time slices, through the entire resonant extraction cycle of nominally 43 msec. The Mu2E tune meter system utilizes vertical and horizontal 21.4 MHz Schottky detector resonant pickups, taken from the decommissioned Tevatron, high-gain amplifiers and digital down-conversion FPGA logic for its signal processing. This paper will present the design of this Schottky tune meter as well as tune measurements from the Mu2E delivery ring.

43 PARTICLE ACCELERATORS↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2023

Oak Ridge National Laboratory Security by Design: A Plant Design and Component-Based Approach to Technical Solutions to Insider and Outsider Threat

Security costs for nuclear reactors have been shown to rise over the lifecycle of a nuclear facility as new threats, security weaknesses, and the generic threat profile of the plant location change over time. This paper conducts a review of the technological gaps that currently exist in Security by Design (SeBD) based on the literature available and attempts to close those gaps through proposing technological constructs and processes that can integrate safety and security in the design process of a plant, with a primary focus on SMR technology. Under the new modular and mass manufacturing regime, where plant designs attempt to reduce costs with potential economies of scale and modular construction, the current SeBD definitions focusing on state level regulators are not considered adequate since the licensing stage is often too late in the design process to integrate the true cost savings of SeBD. Thus, this paper attempts to remedy the current logic in order to allow for continuous implementation of security alongside the development of the safety concept for the plant. If adopted within the design process the establishment of this type of technology will allow for a technological ecosystem to evolve that will imbed security concepts into the physical design of the components of the plant.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2025

Three-Dimensional Bubble Fluidics in Architected Porous Media

Gas bubble flows in porous media often exhibit complex and seemingly unpredictable behaviors that are difficult to control. This lack of control limits the ability to design effective devices which manage multiphase flows. Here, we show how the design of 3D printed pores can deterministically control the flow path of an injected gas stream. Open cell structures can be designed to shape the gas/liquid interface with fidelity to control how the two phases are distributed throughout a porous material. The distributed gas volume is free to interact physically and chemically with the surrounding liquid phase, an effect we exploit to create a logical control gate to redirect flows within a lattice. This also allows us to design architectures for reactive capture and aerating bioreactors, resulting in patterned boundaries which can make more effective use of the liquid and gas reagents.

3D microfluidics↗
DOE OSTI2024

LENS: Learning Enabled Network Synthesis

RTRC and UMD have developed novel machine learning based methods under the ARPA-E DIFFERENTIATE program for rapid acceleration of hypothesis generation in complex architecture design spaces involving both discrete choices of component inclusion and interconnection and continuous parametric decisions. The project named Learning Enabled Network Synthesis (LENS) further demonstrated the developed methods on challenging electrical power converter design problems by identifying the most suitable circuit topologies and simultaneously selecting the most appropriate components to achieve optimized design of power converter with improved performances. We demonstrated that LENS could enable exploration of very large design space of circuit topologies and components by addressing the limitations of conventional design process in non-linear, high switching speed, multi-dimensional power converter design and optimization. The key innovation developed in LENS is the seamless integration of statistical learning and logical reasoning techniques and building on the individual strengths of these techniques for rapid hypothesis discovery. The main component of LENS comprises of: 1) Graph Reasoning Engine (GRE) to enforce composition rules that rapidly reject all discrete architectures that are composed incorrectly and generates an adaptive database of feasible designs which can be used by ML modules, 2) Graph Generative Learning module which is a deep neural network based generative model for graph architectures which can enable design space exploration beyond the dataset generated by the GRE, 3) Graph Reduced Order Model (ROM) for graph domains for accelerating computation of output metrics, and 4) Active learning and Rule Discovery module for sample efficient learning and extracting logical rules from the learned ML models which will be integrated in the GRE to enhance the filtering effectiveness. LENS approach can be applied to any design domains where designs can be represented as multi-attribute graphs. The LENS team integrated the various technical innovations listed above into an optimization pipeline and exercised the optimization pipeline on the converter design problem. The LENS project demonstrated that the developed AI/ML technologies can be used to generate novel converter circuits >45x faster than experts on chosen use-cases. This can enable faster design space exploration and identification of new designs which are not considered by experts due to the increasing design space complexity. This has significant potential impact on the public and energy needs of the country. It is currently estimated that 30% of all electrical powers generated passes through power converters. The future estimate is that 80% of all power generated would be passing through converters. LENS fills a critical gap in this space since by accelerating the design process the designers would be able to generate more efficient converters which can lead to significant energy savings for the country.

42 ENGINEERING↗
DOE OSTI2022

All‐Polymer Bulk‐Heterojunction Organic Electrochemical Transistors with Balanced Ionic and Electronic Transport

Abstract The rapid development of organic electrochemical transistor (OECTs)‐based circuits brings new opportunities for next‐generation integrated bioelectronics. The all‐polymer bulk‐heterojunction (BHJ) offers an attractive, inexpensive alternative to achieve efficient ambipolar OECTs, and building blocks of logic circuits constructed from them, but have not been investigated to date. Here, the first all‐polymer BHJ‐based OECTs are reported, consisting of a blend of new p‐type ladder conjugated polymer and a state‐of‐the‐art n‐type ladder polymer. The whole ladder‐type polymer BHJ also proves that side chains are not necessary for good ion transport. Instead, the polymer nanostructures play a critical role in the ion penetration and transportation and thus in the device performance. It also provides a facile strategy and simplifies the fabrication process, forgoing the need to pattern multiple active layers. In addition, the development of complementary metal–oxide–semiconductor (CMOS)‐like OECTs allows the pursuit of advanced functional logic circuitry, including inverters and NAND gates, as well as for amplifying electrophysiology signals. This work opens a new approach to the design of new materials for OECTs and will contribute to the development of organic heterojunctions for ambipolar OECTs toward high‐performing logic circuits.

Chemistry↗
DOE OSTI2020

Genetic circuit characterization by inferring RNA polymerase movement and ribosome usage

To perform their computational function, genetic circuits change states through a symphony of genetic parts that turn regulator expression on and off. Debugging is frustrated by an inability to characterize parts in the context of the circuit and identify the origins of failures. Here, we take snapshots of a large genetic circuit in different states: RNA-seq is used to visualize circuit function as a changing pattern of RNA polymerase (RNAP) flux along the DNA. Together with ribosome profiling, all 54 genetic parts (promoters, ribozymes, RBSs, terminators) are parameterized and used to inform a mathematical model that can predict circuit performance, dynamics, and robustness. The circuit behaves as designed; however, it is riddled with genetic errors, including cryptic sense/antisense promoters and translation, attenuation, incorrect start codons, and a failed gate. While not impacting the expected Boolean logic, they reduce the prediction accuracy and could lead to failures when the parts are used in other designs. Finally, the cellular power (RNAP and ribosome usage) required to maintain a circuit state is calculated. This work demonstrates the use of a small number of measurements to fully parameterize a regulatory circuit and quantify its impact on host.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.

cryogenic optimization↗
DOE OSTI2021

A-SST Initial Specification

The U.S. Army Research Office (ARO), in partnership with IARPA, are investigating innovative, efficient, and scalable computer architectures that are capable of executing next-generation large scale data-analytic applications. These applications are increasingly sparse, unstructured, non-local, and heterogeneous. Under the Advanced Graphic Intelligence Logical computing Environment (AGILE) program, Performer teams will be asked to design computer architectures to meet the future needs of the DoD and the Intelligence Community (IC). This design effort will require flexible, scalable, and detailed simulation to assess the performance, efficiency, and validity of their designs. To support AGILE, Sandia National Labs will be providing the AGILE-enhanced Structural Simulation Toolkit (A-SST). This toolkit is a computer architecture simulation framework designed to support fast, parallel, and multi-scale simulation of novel architectures. This document describes the A-SST framework, some of its library of simulation models, and how it may be used by AGILE Performers.

97 MATHEMATICS AND COMPUTING↗