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We describe a method for achieving arbitrary 1-qubit gates and controlled-NOT gates within the context of the Single Cooper Pair Box (SCB) approach to quantum computing. Such gates are sufficient to support universal quantum computation.
A gate drive latching circuit for an auxiliary resonant commutation circuit for a power switching inverter includes a current monitor circuit providing a current signal to a pair of analog comparators to implement latching of one of a pair of auxiliary switching devices which are used to provide commutation current for commutating switching inverters in the circuit. Each of the pair of comparators feeds a latching circuit which responds to an active one of the comparators for latching the associated gate drive circuit for one of the pair of auxiliary commutating switches. An initial firing signal is applied to each of the commutating switches to gate each into conduction and the resulting current is monitored to determine current direction and therefore the one of the switches which is carrying current. The comparator provides a latching signal to the one of the auxiliary power switches which is actually conducting current and latches that particular power switch into an on state for the duration of current through the device. The latching circuit is so designed that the only time one of the auxiliary switching devices can be latched on is during the duration of an initial firing command signal.
Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR susceptibility is explored. SEGR evaluation of gamma-irradiated power MOSFETs suggests a non-significant SEGR susceptibility enhancement due to accumulated dose from gamma rays. During SEGR testing, an unexpected enhanced dose effect from heavy-ion irradiation was detected. We demonstrate that this effect could be due to direct ionization by two or more ions at the same channel location. The probability on-orbit for such an occurrence is near-zero given the low heavy-ion fluence over a typical mission lifetime, and did not affect SEGR susceptibility. The results of this work can be used to bound the risk of SEGR in power MOSFETs considered for insertion into spacecraft and instruments.
A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.
MscL is a channel that opens a large pore in the Escherichia coli cytoplasmic membrane in response to mechanical stress. Previously, we highly enriched the MscL protein by using patch clamp as a functional assay and cloned the corresponding gene. The predicted protein contains a largely hydrophobic core spanning two-thirds of the molecule and a more hydrophilic carboxyl terminal tail. Because MscL had no homology to characterized proteins, it was impossible to predict functional regions of the protein by simple inspection. Here, by mutagenesis, we have searched for functionally important regions of this molecule. We show that a short deletion from the amino terminus (3 amino acids), and a larger deletion of 27 amino acids from the carboxyl terminus of this protein, had little if any effect in channel properties. We have thus narrowed the search of the core mechanosensitive mechanism to 106 residues of this 136-amino acid protein. In contrast, single residue substitutions of a lysine in the putative first transmembrane domain or a glutamine in the periplasmic loop caused pronounced shifts in the mechano-sensitivity curves and/or large changes in the kinetics of channel gating, suggesting that the conformational structure in these regions is critical for normal mechanosensitive channel gating.
Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. TheSCF9550 from Semicoa and the IRHM57260SE from International Rectifier were tested to NASA test condition/standards and requirements.The IRHM57260SE performed much better when compared to previous testing. These initial results confirm that parts from the Temecula line are marginally comparable to the El Segundo line. The SCF9550 from Semicoa was also tested and represents the initial parts offering from this vendor. Both parts experienced single-event gate rupture (SEGR) and single-event burnout (SEB). All of the SEGR was from gate to drain.
An Integrated Gate Turnaround Management (IGTM) prototype was developed at NASA Ames Simulation Laboratories (SimLabs) using Dallas Ft. Worth International Airport (DFW) to demonstrate the IGTM concepts feasibility and benefits. The simulation architecture includes: the IGTM controller, an Airline Operations Control (AOC) application, Big DataAnalytics Input (BAI) application, a terminal traffic simulation or known as NASA-developed Surface Operation Simulator and Scheduler (SOSS), and a Database Server. ActiveMQ, a Java messaging service, was used to emulate the System Wide Information Management (SWIM) data network messaging. This paper describes the modeling and simulation of the IGTM concept, and illustrates selected use cases to demonstrate the feasibility and benefits of the IGTM concept for optimizing gate turnaround operations.
Emerging power metal-oxide semiconductor field-effect transistor (MOSFETs) based on silicon carbide and gallium nitride technology are finding widespread use in many electronic applications such as motor control and DC/DC converters due to their higher voltage, higher temperature tolerance, and higher frequency switching capabilities. To utilize these power devices and to meet circuit/system compactness, modularity, and operational functionality, gate drivers that provide unique attributes, such as fast switching and high-current handling capability, are needed. In addition, power systems geared for use in space mission applications require on-board devices to withstand exposure to extreme temperatures and wide thermal swings. Very little data, however, exist on the performance of such devices and circuits under extreme temperatures. In this work, the performance of a high-speed gate driver with potential use in controlling power-level transistors was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.
NASA is conducting the Airspace Technology Demonstration-2 to evaluate an Integrated Arrival, Departure, and Surface (IADS) traffic management system. The IADS system is powered by real-time System Wide Information Management feeds which provide an accurate and high fidelity view of the lifecycle of a flight. This data can be leveraged to drive efficiencies in the National Airspace System. For non safety critical applications there is opportunity for third party service providers to offer this type of data-driven prediction service in near real-time. This paper investigates the gate conflict prediction problem as a concrete use case which could help drive efficiencies. We model gate conflicts as a regression problem and describe the iterative process of model building, model validation, and evaluation used to assess the efficacy of our approach. We quantify our predictive accuracy and identify paths for improvement. Through this iterative process we hope to evolve our models and methods to a near real-time prediction service.
Photoemission spectra of a GaAs gate material of a metal semiconductor field effect transistor (MESFET) were analyzed to nondestructively assess the submicron-size local gate temperature.
A copper base insert coated with a layer of aluminum oxide ceramic prevents frictional binding between the gate and base surfaces of a gate valve which are subject to rapid sliding action and high temperatures.
Improved magnetometer employs a cylindrical, high permeability magnetic core with a toroidal gating coil and a solenoid pickup coil. Flux interaction can be reduced by electrostatically shielding the pickup coil from the gating coil. The magnetometer principle can be applied to navigation devices.
Standard dosimeter reader, modified by adding an electronic gating circuit to trigger the intensity level photomultiplier, increases readout sensitivity of photoluminescent dosimeter systems. The gating circuit is controlled by a second photomultiplier which senses a short ultraviolet pulse from a laser used to excite the dosimeter.
Flux gate magnetometer with toroidal gating coil and solenoidal output coil for signal modulation or amplification
Silicon controlled rectifier pulse gate amplifier for blocking false gating caused by negative transient voltages
The construction and use are described for a radioactive calibration source that produces an electronic gating pulse when a calibration gamma ray is emitted and makes it possible to employ this source in many calibration or stabilizing tasks without the disadvantage of having to introduce extra counts into the unknown spectrum. The described source is radioactively safe, easy to construct, and has the ability of producing gating efficiencies as high as 98%.
A distortionless gated compressor for limiting the amplitude of a signal so as not to produce undesired signal levels responsive thereto is disclosed. The gated compressor includes a distortionless multiplier which multiplies an AC signal from a factor defined by a DC control signal. The compressor includes a plurality of channels each responsive to a signal produced in response to the multiplier's output. When the signal supplied to any channel exceeds a prescribed level, the level of the DC control signal is reduced to reduce the multiplier's output level and thereby prevent the signal applied to any channel from exceeding its prescribed level.