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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

Abstract In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

Instruments & Instrumentation↗
DOE OSTI2025

The CMS Phase-2 Fast Beam Condition Monitor prototype test with beam

The Fast Beam Condition Monitor (FBCM) is a standalone luminometer for the High Luminosity LHC (HL-LHC) program of the CMS Experiment at CERN. The detector is under development and features a new, radiation-hard, front-end application-specific integrated circuit (ASIC) designed for beam monitoring applications. The achieved timing resolution of a few nanoseconds enables the measurement of both the luminosity and the beam-induced background. The ASIC, called FBCM23, features six channels with adjustable shaping times, enabling in-field fine-tuning. Each ASIC channel outputs a single binary asynchronous signal encoding time-of-arrival and time-over-threshold information. The FBCM is based on silicon-pad sensors, with two sensor designs presently being considered. This paper presents the results of tests of the FBCM detector prototype using both types of silicon sensors with hadron, muon, and electron beams. Irradiated FBCM23 ASICs and silicon-pad sensors were also tested to simulate the expected conditions near the end of the detector's lifetime in the HL-LHC radiation environment. Based on test results, direct bonding between the sensor and ASIC was chosen, and an optimal bias voltage and ASIC threshold for FBCM operation were proposed. The current design of the front-end test board was validated following the beam test and is now being used for the first front-end module, which is expected to be produced in summer 2025. These results represent a major step forward in validating the FBCM concept, first version of the firmware and establishing a reliable design path for the final detector.

Beam-line instrumentation (beam position and profi↗
DOE OSTI2020

Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml

We present the implementation of binary and ternary neural networks in the hls4ml library, designed to automatically convert deep neural network models to digital circuits with FPGA firmware. Starting from benchmark models trained with floating point precision, we investigate different strategies to reduce the network's resource consumption by reducing the numerical precision of the network parameters to binary or ternary. We discuss the trade-off between model accuracy and resource consumption. In addition, we show how to balance between latency and accuracy by retaining full precision on a selected subset of network components. As an example, we consider two multiclass classification tasks: handwritten digit recognition with the MNIST data set and jet identification with simulated proton-proton collisions at the CERN Large Hadron Collider. The binary and ternary implementation has similar performance to the higher precision implementation while using drastically fewer FPGA resources.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Strengthening Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-Based Infrastructure

In this paper, we propose two new approaches aimed at enhancing the security of industrial control systems (ICS) that utilize programmable logic controllers (PLCs) for the control of critical processes. The first approach involves the addition of a unique digital watermark to the PWM control that adjusts the motor speed to control the critical process. This enables efficient detection and identification of any unauthorized modifications to the sensor signals responsible for controlling the plant. The second approach focuses on monitoring the input current (i.e power) drawn by the PLC during the execution of critical process control tasks. Malicious intrusions to change the PLC parameters and/or unauthorized firmware updates can be rapidly detected. Both approaches demonstrate a substantial improvement in the security of ICS, effectively safeguarding against potential cyber-attacks. Experimental results from a laboratory scale water tank level controlled via PLC showcases rapid intrusion detection capabilities.

Huang, Peng-Hao↗
DOE OSTI2025

Obstacles to Practical Digital Supply Chain Risk Management in the Energy Sector

Cyber supply chain risk management (C-SCRM) programs must consider operations that depend on the lifecycles of digital components such as hardware, firmware, software, and services. We integrate academic literature, historical incidents, and existing standards to identify obstacles faced by C-SCRM programs.

Business Process Management & Integration↗
DOE OSTI2021

Security Vulnerability and Mitigation in Photovoltaic Systems

Software and firmware vulnerabilities pose security threats to photovoltaic (PV) systems. When patches are not available or cannot be timely applied to fix vulnerabilities, it is important to mitigate vulnerabilities such that they cannot be exploited by attackers or their impacts will be limited when exploited. However, the vulnerability mitigation problem for PV systems has received little attention. This paper analyzes known security vulnerabilities in PV systems, proposes a multi-level mitigation framework and various mitigation strategies including neural network-based attack detection inside inverters, and develops a prototype system as a proof-of-concept for building vulnerability mitigation into PV system design.

14 SOLAR ENERGY↗
DOE OSTI2023

Prototype Design of Global Common Module for ATLAS Experiment’s Phase-II Upgrade

A new Global Trigger subsystem will be installed in the Level-0 Trigger as part of HL-LHC Upgrade of ATLAS during the upcoming Long-Shutdown 3. It will feature new and improved trigger hardware and algorithms, and an increased maximum output rate of 1 MHz. The Global Trigger will run offline-like trigger algorithms on full-granularity data, gathered from several sub-detectors and trigger-processing subsystems. A single Global Common Module (GCM) hardware is implemented across the Global Trigger system to be used as Multiplexer Processor, Global Event Processor and CTP Interface (gCTPi). This common hardware platform method will minimize the complexity of the firmware and simplify the system design and long-term maintenance. The GCM prototype is an ATCA front form factor board with two Xilinx Virtex UltraScale+ FPGA VU13P and one ZYNQ UltraScale+ FPGA ZU19EG and seventeen 25.78125 Gb/s FireFly duplex optical modules on it. The total power consumption of this board must be less than 350 W, and the temperature of the optical modules should be less than 70 °C in the worst case. The VU13Ps serve as algorithms processor nodes such as MUX, GEP and gCTPi, and the ZU19EG with Peta Linux OS running on it, is used as Command/Control/Readout Unit to configure and monitor the board and communicate with the ATLAS Detector Control System (DCS). The development of an ATCA blade with three large FPGAs and about 200 optical links running at 25Gb/s is a very challenging task, and the successful test results have demonstrated this GCM prototype as an advancement of state-of-the-art electronics module design in HEP experiments. This paper presents the hardware design considerations, functionalities, and performance test results of this GCM prototype.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

End-to-End Workflow for Machine-Learning-Based Qubit Readout With QICK and hls4ml

In this article, we present an end-to-end workflow for superconducting qubit readout that embeds codesigned neural networks into the quantum instrumentation control kit (QICK). Capitalizing on the custom firmware and software of the QICK platform, which is built on Xilinx radiofrequency system-on-chip field-programmable gate arrays (FPGAs), we aim to leverage machine learning (ML) to address critical challenges in qubit readout accuracy and scalability. The workflow utilizes the hls4ml package and employs quantization-aware training to translate ML models into hardware-efficient FPGA implementations via user-friendly Python application programming interfaces. We experimentally demonstrate the design, optimization, and integration of an ML algorithm for single transmon qubit readout, achieving 96% single-shot fidelity with a latency of 32.25 ns and less than 16% FPGA lookup table resource utilization. Our results offer the community an accessible workflow to advance ML-driven readout and adaptive control in quantum information processing applications.

42 ENGINEERING↗
DOE OSTI2020

Octet: A coherent qubit control system for trapped-ion quantum computers

This is firmware and software designed for a Zynq UltraScale+ RFSoC chip made by Xilinx, specifically targeted to laser-based individual addressing of trapped ion qubits via a multi-channel AOM. The design features 8 dual-tone outputs with frequencies up to 409 MHz that can be controlled statically or dynamically via on-chip cubic spline interpolation engines that allow one to generate sequences of output waveforms with fast modulation of frequency, phase, amplitude, and z-rotations that are smooth/discrete and can run simultaneously across all parameters/tones. It also features global phase alignment on all tones regardless of frequency and the ability to return to a known phase/frequency at any later time on a per-tone basis without the need for manual bookkeeping. Acoustic and optical cross-talk can also be destructively canceled by adding neighboring outputs with variable amplitude/phase/delay. Each tone can be optionally frequency locked to an external RF source. SAND2020-12703 M Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Lobser, Daniel↗
DOE OSTI2021

LBNL Cell controller v1.0

Firmware and software of LBNL's Cell controller logic. Cell logic forms a high-speed data distribution network of FPGAs, transmitting data in a ring topology. This logic is used at ALS for the distribution of BPM data as part of the fast orbit feedback system.

Norum, William↗
DOE OSTI2022

initAnalysis

A tool to quickly perform recon in the init process of a given firmware.

Craig, Chris↗
DOE OSTI2020

slaclab/cpswTreeGUI

Graphical User Interface based on CPSW to interact with a Firmware register tree.

Vasquez, Jesus↗
DOE OSTI2021

slaclab/cryo-wib-firmware

This is the repository for "cryo-wib-firmware" developed by SLAC National Accelerator Laboratory.

Doering, Dionisio↗
DOE OSTI2022

Idaho National Laboratory Data Acquisition And Processing System

The INLDAS data acquisition and processing system is designed to develop prototype measurements and real-time processing techniques. The INLDAS hardware and firmware currently consists of National Instruments • NI-DAQmx 14.1 • cDAQ-9184 • 9205 • 9211 INLDAS can perform of standard data acquisition functions as well as novel functions and real-time processing algorithms. There are 3 acquisition modes to choose from: • Continuous mode runs when the user hits start, processing data and logging it to file • SWTrigger mode waits for one or more predefined triggers before acquiring data. It will buffer data as well, so it can record data that happened shortly before the trigger • Wakeup mode waits on predefined timers. When a time goes off, it acquires a preset amount of data There are also 3 Data Processing Modes • Normal mode does no processing besides the rolling average • FFT Mode Performs an FFT on incoming data every time the time window has elapsed • STFFT mode

Smith, JamesA↗
DOE OSTI2022

Direct-Sampling Beam Position Monitor (dsbpm) v1.0

Direct-Sampling Beam Position Monitor is an FPGA gateware and embedded firmware that run on evaluation kits (either Xilinx ZCU111 or Xilinx ZCU208 ) that digitizes signals up to 4GSPS and 4GHz analog bandwidth, which can be synchronized to the accelerator timing system, providing synchronous sampling frequency/phase digitization. In addition to these capabilities, a proof of concept for a beam position monitor is also present, providing an envelope detection algorithm capable of determining the transverse beam position for an electron circular accelerator, such as ALS/ALS-U.

Norum, William↗
DOE OSTI2025

OPET Hardware (Open PV Electrical Tool Hardware) [SWR-25-42]

OPET (Open-source Photovoltaic Electrical Tool) is used for performance measurements of solar photovoltaic (PV) devices in the field under natural sunlight or in the lab under artificial light. Its primary use is in research and development of solar cells and modules, specifically in reliability and durability research of PV devices. Some features and functions include: -IV curve measurements with linear or cosine distributed measurement points -PV device active loading at open circuit voltage (Voc), short circuit current (Isc) and maximum power point (Pmp) -Bias power supply to overcome series resistance in contact wires for Isc measurements and loading -PV voltage input in five ranges from 1V to 100V -PV current input ranges -Low current version, six current ranges from 1.1mA to 340mA -High current version, six current ranges from 50mA to 15A -IO ports for I2C and SPI temperature sensor Arduino extension boards -Integrated fan control This repository contains everything relating to the hardware of the OPET device. If you are looking for the firmware or software repositories, links are below: https://github.com/NREL/opet-firmware https://github.com/NREL/opet-control

McDanold, Byron [National Renewable Energy Laborat↗