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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

Models of second-order effects in metal-oxide-semiconductor field-effect transistors for computer applications

Second-order effects in metal-oxide-semiconductor field-effect transistors (MOSFETs) are important for devices with dimensions of 2 microns or less. The short and narrow channel effects and drain-induced barrier lowering primarily affect threshold voltage, but formulas for drain current must also take these effects into account. In addition, the drain current is sensitive to channel length modulation due to pinch-off or velocity saturation and is diminished by electron mobility degradation due to normal and lateral electric fields in the channel. A model of a MOSFET including these considerations and emphasizing charge conservation is discussed.

Benumof, Reuben↗
NASA NTRS2013

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Hunt, Mitchell↗
NASA NTRS1987

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗
NASA NTRS1991

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

Kapoor, V. J.↗
NASA NTRS2004

Design of an Auto-zeroed, Differential, Organic Thin-film Field-effect Transistor Amplifier for Sensor Applications

Organic strain gauge and other sensors require high-gain, precision dc amplification to process their low-level output signals. Ideally, amplifiers would be fabricated using organic thin-film field-effect transistors (OTFT's) adjacent to the sensors. However, OTFT amplifiers exhibit low gain and high input-referred dc offsets that must be effectively managed. This paper presents a four-stage, cascaded differential OTFT amplifier utilizing switched capacitor auto-zeroing. Each stage provides a nominal voltage gain of four through a differential pair driving low-impedance active loads, which provide common-mode output voltage control. p-type pentacence OTFT's are used for the amplifier devices and auto-zero switches. Simulations indicate the amplifier provides a nominal voltage gain of 280 V/V and effectively amplifies a 1-mV dc signal in the presence of 500-mV amplifier input-referred dc offset voltages. Future work could include the addition of digital gain calibration and offset correction of residual offsets associated with charge injection imbalance in the differential circuits.

large-area electronics↗
NASA NTRS1992

Study of InGaAs-based modulation doped field effect transistor structures using variable-angle spectroscopic ellipsometry

Variable-angle spectroscopic ellipsometry was used to estimate the thicknesses of all layers within the optical penetration depth of InGaAs-based modulation doped field effect transistor structures. Strained and unstrained InGaAs channels were made by molecular beam epitaxy (MBE) on InP substrates and by metal organic chemical vapor deposition on GaAs substrates. In most cases, ellipsometrically determined thicknesses were within 10 percent of the growth-calibration results. The MBE-made InGaAs strained layers showed large strain effects, indicating a probable shift in the critical point of their dielectric function toward the InP lattice-matched concentration.

Alterovitz, Samuel A.↗
NASA NTRS1991

Study of InGaAs-based modulation doped field effect transistor structures using variable-angle spectroscopic ellipsometry

Variable-angle spectroscopic ellipsometry was used to estimate the thicknesses of all layers within the optical penetration depth of InGaAs-based modulation doped field effect transistor structures. Strained and unstrained InGaAs channels were made by molecular beam epitaxy (MBE) on InP substrates and by metal-organic chemical vapor deposition on GaAs substrates. In most cases, ellipsometrically determined thicknesses were within 10% of the growth-calibration results. The MBE-made InGaAs strained layers showed large strain effects, indicating a probable shift in the critical points of their dielectric function toward the InP lattice-matched concentration.

Alterovitz, S. A.↗
NASA NTRS1973

Gyrator employing field effect transistors

A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Hochmair, E. S.↗
NASA NTRS1983

High-performance K-band GaAs power field-effect transistors prepared by molecular beam epitaxy

The maturity of the molecular beam epitaxy (MBE) technique for preparing device quality GaAs material for microwave applications is demonstrated by the excellent performance characteristics of K-band GaAs power field-effect transistors (FETs) fabricated on the MBE wafers. An output power of 710 mW with 4.5-dB gain and 17.7 percent power-added efficiency was achieved at 21 GHz with a 1.26-mm gate width pi-gate device. A similar device with a 0.56-mm gate width produced an output power of 320 mW with 5.0-dB gain and 26.6 percent power-added efficiency at 21 GHz. These are the best results yet reported to date for GaAs power FETs operated in the K-band frequency range.

Saunier, P.↗
NASA NTRS1993

Characteristics of 0.8- and 0.2-microns gate length In(x)Ga(1-x) As/In(0.52)Al(0.48)As/InP (0.53 less than or equal to x less than or equal to 0.70) modulation-doped field-effect transistors at cryogenic temperatures

The performance characteristics of InP-based In(x)Ga(1-x)As/In(0.52)Al(0.48)As (0.53 is less than or equal to x is less than or equal to 0.70) pseudomorphic modulation-doped field-effect transistors (MODFET's) as a function of strain in the channel, gate, length, and temperature were investigated analytically and experimentally. The strain in the channel was varied by varying the In composition x. The temperature was varied in the range of 40-300 K and the devices have gate lengths L(sub g) of 0.8 and 0.2 microns. Analysis of the device was done using a one-dimensional self consistent solution of the Poisson and Schroedinger equations in the channel, a two-dimensional Poisson solver to obtain the channel electric field, and a Monte Carlo simulation to estimate the carrier transit times in the channel. An increase in the value of the cutoff frequency is predicted for an increase in In composition, a decrease in temperature, and a decrease in gate length. The improvements seen with decreasing temperature, decreasing gate length, and increased In composition were smaller than those predicted by analysis. The experimental results on pseudomorphic InGaAs/InAlAs MODFET's showed that there is a 15-30 percent improvement in cutoff frequency in both the 0.8- and 0.2-micron gate length devices when the temperature is lowered from 300 to 40 K.

Lai, Richard↗
NASA NTRS2006

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

MacLeod, Todd, C.↗
NASA NTRS2006

SiC Field Effect Transistor Technology Demonstrating Prolonged Stable Operation at 500 C

While there have been numerous reports of short-term transistor operation at 500 degree C or above, these devices have previously not demonstrated sufficient long-term operational durability at 500 degree C to be considered viable for most envisioned applications. This paper reports the development of Silicone Carbi field effect transistors capable of long-term electrical operation at 500 degree C. A 6H-SiC MESFET was packaged and subjected to continuous electrical operation while residing in a 500 degree C oven in oxidizing air atmosphere for over 2400 hours. The transistor gain, saturation current (IDSS), and on-resistance (RDS) changed by less than 20% from initial values throughout the duration of the biased 500 degree C test. Another high-temperature packaged 6H-SiC MESFET was employed to form a simple one-stage high-temperature low-frequency voltage amplifier. This single-stage common-source amplifier demonstrated stable continuous electrical operation (negligible changes to gain and operating biases) for over 600 hours while residing in a 500 degree C air ambient oven. In both cases, increased leakage from annealing of the Schottky gate-to-channel diode was the dominant transistor degradation mechanism that limited the duration of 500 degree C electrical operation.

Neudeck, Philip G.↗
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗
NASA NTRS2004

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Demonstrated

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decisionmaking ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline/polyethylene oxide (PANi/PEO) nanofibers are of interest because they have electrical conductivities that can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain. At the NASA Glenn Research Center, we have observed field effect transistor (FET) behavior in electrospun PANi/PEO nanofibers doped with camphorsulfonic acid. The nanofibers were deposited onto Au electrodes, which had been prepatterned onto oxidized silicon substrates. The preceding scanning electron image shows the device used in the transistor measurements. Saturation channel currents are observed at surprisingly low source/drain voltages (see the following graph). The hole mobility in the depletion regime is 1.4x10(exp -4)sq cm/V sec, whereas the one-dimensional charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx.10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating one-dimensional polymer FET's.

Mueller, Carl H.↗
NASA NTRS2002

Cryogenetically Cooled Field Effect Transistors for Low-Noise Systems

Recent tends in the design, fabrication and use of High-Electron-Mobility-Transistors (HEMT) in low noise amplifiers are reviewed. Systems employing these devices have achieved the lowest system noise for wavelengths greater than three millimeters with relatively modest cryogenic cooling requirements in a variety of ground and space based applications. System requirements which arise in employing such devices in imaging applications are contrasted with other leading coherent detector candidates at microwave wavelengths. Fundamental and practical limitations which arise in the context of microwave application of field effect devices at cryogenic temperatures will be discussed from a component and systems point of view.

Wollack, Edward J.↗