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This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).
The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.
Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.
Molecules based on benzimidazolone-dioxazine are known as blue/violet pigments and have been commercialized for decades. However, unfavorable solubility limits the application of these structures as building blocks of conjugated polymers despite their low band gaps. Herein, a series of donor–acceptor conjugated polymers containing soluble benzimidazolone-dioxazine structures as the acceptors and oligothiophene as donors are synthesized and investigated. With increasing numbers of thiophene rings, the steric hindrance diminishes and high molecular weight polymers can be achieved, leading to an improved performance in organic field effect transistor devices. The hole mobility of polymers with three to six thiophene units is in the order of 10 -1 cm2 V -1 s -1 . Among all the polymers, polymer P3 with three thiophene units between benzimidazolone-dioxazine structures shows the best hole mobility of 0.4 cm2 V -1 s -1 . Grazing-incidence wide-angle X-ray scattering results reveal that the high mobility of organic field-effect transistors (OFETs) can be accredited by matched donor–acceptor packing in the solid thin films.
Excellent dc and millimeter-wave performance is reported in In0.15Ga0.85As/Al0.15Ga0.85As pseudomorphic modulation-doped field effect transistors (MODFET's) with 0.25-micron-length gates. Extrinsic transconductances as high as 495 mS/mm at 300 K and unprecedented power performance in the 60-GHz range were observed. Although not yet optimized, excellent low noise characteristics, 0.9 dB, with an associated gain of 10.4 dB at 18 GHz, and a noise figure of 2.4 dB with an associated gain of 4.4 dB at 62 GHz were obtained. This is the best noise performance ever reported for a MODFET in this frequency range. These results clearly demonstrate the superiority of pseudomorphic MODFET structures in high-frequency applications.
A single-stage C-band superconductor/semiconductor hybrid field-effect transistor amplifier was designed, fabricated, and tested at 77 K. The large area (1 inch x 0.5 inches) high temperature superconducting Tl-Ba-Ca-Cu-O (TBCCO) thin film was rf magnetron sputtered onto a LaAlO3 substrate. The film had a transition temperature of about 92 K after it was patterned and etched. The amplifier showed a gain of 6 dB and a 3 dB bandwidth of 100 MHz centered at 7.9 GHz. An identical gold amplifier circuit was tested at 77 K, and these results are compared with those from the hybrid amplifier.
The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.
Differential drain resistance calculation for junction field effect transistors
A model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. The model is based on an existing model that incorporates partitioning of the ferroelectric layer to calculate the polarization within the ferroelectric material. The model incorporates several new aspects that are useful to the user. It takes into account the effect of a non-saturating gate voltage only partially polarizing the ferroelectric material based on the existing remnant polarization. The model also incorporates the decay of the remnant polarization based on the time history of the FFET. A gate pulse of a specific voltage; will not put the ferroelectric material into a single amount of polarization for that voltage, but instead vary with previous state of the material and the time since the last change to the gate voltage. The model also utilizes data from FFETs made from different types of ferroelectric materials to allow the user just to input the material being used and not recreate the entire model. The model also allows the user to input the quality of the ferroelectric material being used. The ferroelectric material quality can go from a theoretical perfect material with little loss and no decay to a less than perfect material with remnant losses and decay. This model is designed to be used by people who need to predict the external characteristics of a FFET before the time and expense of design and fabrication. It also allows the parametric evaluation of quality of the ferroelectric film on the overall performance of the transistor.
Nano-membrane tri-gate β-gallium oxide (β-Ga 2 O 3 ) field-effect transistors (FETs) on SiO 2 /Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β-Ga 2 O 3 and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al 2 O 3 ) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV dec –1 , high drain current (I DS ) ON/OFF ratio of 1.5 × 10 9 , and negligible transfer characteristic hysteresis. Furthermore, we also experimentally demonstrated robustness of these devices with current–voltage (I–V) characteristics measured at temperatures up to 400 °C.
A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.
Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.
Widespread, persistent and toxic per- and polyfluoroalkyl substances (PFAS) pose a major threat to water systems and human health. Current detection methods are relatively expensive, slow and complex, underscoring the need for more accessible alternatives to meet increasingly stringent PFAS regulations. Here, in this study, we present an ultrasensitive sensing platform for perfluorooctane sulfonic acid detection in tap water with a reporting limit ( ~ 250 parts per quadrillion) lower than the US Environmental Protection Agency’s regulatory standard (4 parts per trillion), using a remote gate field-effect transistor featuring β-cyclodextrin (β-CD)-modified reduced graphene oxide as the sensing membrane. The sensor exhibits excellent selectivity against common inorganic ions, natural organic matter and select organic pollutants in tap water. The reversible and rapid response ( < 2 min) indicates the potential of remote gate field-effect transistor for continuous in-line monitoring. Mechanistic studies using quartz crystal microbalance and molecular dynamics simulations reveal key roles of analyte adsorption and charge properties in sensing performance and offer insights for designing more selective PFAS capture probes.
γ-InSe is a semiconductor that holds promising potential in high-performance field-effect transistors and optoelectronic devices. Large-scale, single-phase γ-InSe deposition has proven challenging because of the difficulty in precise control of stoichiometry and the coexistence of different indium selenide phases. In this study, we demonstrate the wafer-scale combinatorial approach to map out the growth window as functions of the Se/In ratio and growth temperature for γ-InSe on the Si(111) 7 × 7 substrate in molecular beam epitaxy. X-ray diffraction (XRD) was used to identify the indium selenide phases, while atomic force microscopy revealed four distinct surface morphologies of γ-InSe, enabling a discussion of the growth mechanisms associated with each morphology. Cross-sectional atomic resolution scanning transmission electron microscopy confirmed that the film was of high crystalline quality and had nearly single-phase γ-InSe. In conclusion, our comprehensive study elucidates the In–Se phase map for thin film growth parameters, providing invaluable landmarks for the reproducible synthesis of high-quality γ-InSe layers.
Silicon nitride and cermet resistors for binary counter metal insulator field effect transistor circuit
Extremely large current double interface GaAs/In(0.15)Ga(0.85)As/Al(0.15)Ga(0.85)As pseudomorphic modulation-doped field-effect transistors (MODFET's) grown by molecular beam epitaxy were achieved. The 1-micron gate devices studied have peak current levels (430 mA/mm at 300 K and 483mA/mm at 77 K) roughly one and a half to two times that found in single interface pseudomorphic MODFET's. These devices also retain high transconductances over a broad range of gate voltage, peaking at 312 mS/mm at 300 K and 362 mS/mm at 77 K. Excellent microwave performance is also obtained with a maximum frequency of oscillation (f-max) of 37 GHz and a current gain cut-off frequency of as high as 23 GHz at 300 K. An output power level of 14 dBm (1 dB gain compression) was obtained at 6 GHz for a 290-micron gate width. This double interface single quantum well MODFET may be of great importance in millimeter wave power amplifiers.
The metal-to-insulator phase transition (MIT) in low-dimensional materials and particularly two-dimensional layered semiconductors is exciting to explore due to the fact that it challenges the prediction that a two-dimensional system must be insulating at low temperatures. Thus, the exploration of MITs in 2D layered semiconductors expands the understanding of the underlying physics. Here we report the MIT of a few-layered MoSe 2 field effect transistor under a gate bias (electric field) applied perpendicular to the MoSe 2 layers. With low applied gate voltage, the conductivity as a function of temperature from 150 K to 4 K shows typical semiconducting to insulating character. Above a critical applied gate voltage, V c , the conductivity becomes metallic (i.e., the conductivity increases continuously as a function of decreasing temperature). Evidence of a metallic state was observed using an applied gate voltage or, equivalently, increasing the density of charge carriers within the 2D channel. We analyzed the nature of the phase transition using percolation theory, where conductivity scales with the density of charge carriers as σ ∝ (n - n c ) δ . The critical exponent for a percolative phase transition, δ(T), has values ranging from 1.34 (at T = 150 K) to 2 (T = 20 K), which is close to the theoretical value of 1.33 for percolation to occur. Thus we conclude that the MIT in few-layered MoSe 2 is driven by charge carrier percolation. Finally, the conductivity does not scale with temperature, which is a hallmark of a quantum critical phase transition.
Low temperature semiconductor deposition techniques in fabricating thick film, insulated gate, field effect transistors