On-Chip Chromatic Dispersion via Multi-Mode Bragg Gratings: A Design Study
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Lasers↗
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Temperature-tuned ultrafast X-ray shutter using optics-on-a-chip
Typically modulation systems are incapable of performing synchronous modulation for high-energy radiation systems. A method and system for performing high-energy synchronous radiation modulating is described. The method includes providing an oscillatory diffractive element, with the oscillatory diffractive element capable of being oscillated over a range of angles. A radiation source provides radiation to the oscillatory diffractive element. An electrical signal is provided to electrodes that oscillate the oscillatory diffractive element to modulate the radiation. A temperature controller controls the temperature of the oscillatory diffractive element to tune the oscillatory motion of the oscillatory diffractive element.
Wang, Jin↗
On-chip probabilistic inference for charged-particle tracking at the sensor edge
Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.
Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗
Measuring quasiparticle dynamics for particle impact reconstruction in a superconducting qubit chip
Quasiparticle poisoning following particle impacts poses a significant challenge to the development of fault-tolerant superconducting quantum computers, as a sudden excess of quasiparticles can simultaneously degrade the coherence of multiple qubits across large device arrays. In this work, we present a statistical analysis that models the time evolution of radiation-induced qubit energy relaxation through quasiparticle density dynamics. This study provides insight into quasiparticle loss processes by distinguishing between recombination and trapping decay channels and assessing their respective impact on qubit performance. We precisely measure quasiparticle recombination in multiple transmon qubits and uncover an unexpected dependence of qubit relaxation dynamics on deposited energy. By linking correlated relaxation events across qubits to ballistic phonon propagation, we introduce a statistical localization approach to extract the energy deposited in the substrate, which is in good agreement with Monte Carlo simulation. This work establishes the quantitative framework for using an arbitrary subset of superconducting transmon qubits in a QPU as energy-resolving witness particle detectors.
Celi, E. [Northwestern U.]↗
On-Chip Chromatic Dispersion via Multi-Mode Bragg Gratings: A Design Study
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Lasers↗
On-chip GaN Vacuum Electron Devices
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Sapkota, Keshab Raj [Sandia National Laboratories ↗
RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades
The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.
Alimonti, G↗
Scalable Thin Light-Emitting Diode (LED) Light Sheet Platform
The goal of the Scalable Thin Light-Emitting Diode (LED) Light Sheet Platform project is to derisk the manufacturing scalability for a high chip count heterogeneous smart lighting platform, with the potential to enable significant energy savings through dynamic directional light control and custom. Specifically, the project derisks the scalability of a disruptive new computer controlled microassembly fabrication process SRI International is developing, to address fundamental cost barriers to mass production of high chip count systems. This is key for enabling mass adoption and thus maximum societal energy savings impact. The LED light sheet technology is a smart illumination platform that can be applied to lighting, signage, and display. It has features and a form factor similar to bendable or conformal OLED light sheets but uses more efficient LEDs with a remote phosphor layer that is very close to the LED to deliver a luminous efficacy that exceeds 125 lumen/Watt and enable > 50% Lighting Application Efficiency (LAE) energy savings. During Budget Period 1 (BP1), all of the BP1 milestones were successfully completed: (M2.0.1) Design demonstrator details that will meet the final project goals, (M6.1.1) Show lighting output model can predict illuminance, spatial, spectral distribution for specific light-sheet designs and use case, (M3.2.1) Automated loading supports 200 chip arrays, and (M3.3.1) Finish first interconnect process run for 200 chip array. The BP1 Go/No-Go Decision Point (G/NG 1) 200 chip demonstrator sample was in the process of final assembly and test at the end of BP1 on December 31, 2023. The objective was successfully achieved on January 16, 2024, when a wired 200-chip sample underwent confirmation testing that demonstrated a 93.75% first pass electrical yield that successfully exceeded the 75% first-pass electrical yield BP1 G/NG requirement. In addition, all 93.75% of the sample devices lit up, further demonstrating the ability to assemble and transfer small LED chips without damaging their functionality.
32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
Wireless Frequency‐Multiplexed Acoustic Array‐Based Acoustofluidics
Abstract Acoustofluidics has shown great potential in enabling on‐chip technologies for driving liquid flows and manipulating particles and cells for engineering, chemical, and biomedical applications. To introduce on‐demand liquid sample processing and micro/nano‐object manipulation functions to wearable and embeddable electronics, wireless acoustofluidic chips are highly desired. This paper presents wireless acoustofluidic chips to generate acoustic waves carrying sufficient energy and achieve key acoustofluidic functions, including arranging particles and cells, generating fluid streaming, and enriching in‐droplet particles. To enable these functions, the wireless acoustofluidic chips leverage mechanisms, including inductive coupling‐based wireless power transfer (WPT), frequency multiplexing‐based control of multiple acoustic waves, and the resultant acoustic radiation and drag forces. For validation, the wirelessly generated acoustic waves are measured using laser vibrometry when different materials (e.g., bone, tissue, and hand) are inserted between the WPT transmitter and receiver. Moreover, the wireless acoustofluidic chips successfully arrange nanoparticles into different patterns, align cells into parallel pearl chains, generate streaming, and enrich in‐droplet microparticles. This research is anticipated to facilitate the development of embeddable wireless on‐chip flow generators, wearable sensors with liquid sample processing functions, and implantable devices with flow generation and acoustic stimulation abilities for engineering, veterinary, and biomedical applications.
Li, Jiali↗
PSEC5 Physical Verification
Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.
Rico Aniles, H. D. [Unlisted]↗
Microwave-Mediated Extraction of Critical Metals from LED E-Waste
This study introduces a microwave-assisted technique for extracting critical minerals from LED electronic waste. The process begins with microwave irradiation, which thermally decomposes the LED’s plastic lens into a brittle, charred residue. During this stage, the LED chip undergoes deflagration—being rapidly ejected from the reflective cavity and becoming embedded within the decomposed lens material. Consequently, the chip is encapsulated in the resulting charred residue. This composite, consisting of the charred lens and the LED chip, can be easily separated from the metallic pins (Fe, Ni, Ag), which remain almost undamaged. Subsequent calcination of the charred material in air exposes the materials making up the LED chip, which contain critical metals (e.g., Ga, As, In, Y, Au). These metals are then extracted through a two-step acid leaching process involving aqua regia followed by hot concentrated hydrochloric acid, yielding them in potentially recoverable forms. The synergistic effect of microwave irradiation and acid treatment achieves an average extraction efficiency of 96% for critical metals. Notably, this approach enables complete and loss-free recovery of the LED chip, offering a practical and efficient solution for LED e-waste recycling.
Bourlinos, Athanasios B.↗
Incubating advances in integrated photonics with emerging sensing and computational capabilities
As photonic technologies grow in multidimensional aspects, integrated photonics holds a unique position and continuously presents enormous possibilities for research communities. Applications include data centers, environmental monitoring, medical diagnosis, and highly compact communication components, with further possibilities continuously growing. Herein, we review state-of-the-art integrated photonic on-chip sensors that operate in the visible to mid-infrared wavelength region on various material platforms. Among the different materials, architectures, and technologies leading the way for on-chip sensors, we discuss the optical sensing principles that are commonly applied to biochemical and gas sensing. Our focus is on passive optical waveguides, including dispersion-engineered metamaterial-based structures, which are essential for enhancing the interaction between light and analytes in chip-scale sensors. We harness a diverse array of cutting-edge sensing technologies, heralding a revolutionary on-chip sensing paradigm. Our arsenal includes refractive-index-based sensing, plasmonics, and spectroscopy, which forge an unparalleled foundation for innovation and precision. Furthermore, we include a brief discussion of recent trends and computational concepts, incorporating Artificial Intelligence & Machine Learning (AI/ML) and deep learning approaches over the past few years to improve the qualitative and quantitative analysis of sensor measurements.
Jain, Sourabh (ORCID:0000000279923275)↗
In situ counter-diffusion crystallization and long-term crystal preservation in microfluidic fixed targets for serial crystallography
Compared with batch and vapor diffusion methods, counter diffusion can generate larger and higher-quality protein crystals yielding improved diffraction data and higher-resolution structures. Typically, counter-diffusion experiments are conducted in elongated chambers, such as glass capillaries, and the crystals are either directly measured in the capillary or extracted and mounted at the X-ray beamline. Despite the advantages of counter-diffusion protein crystallization, there are few fixed-target devices that utilize counter diffusion for crystallization. In this article, different designs of user-friendly counter-diffusion chambers are presented which can be used to grow large protein crystals in a 2D polymer microfluidic fixed-target chip. Methods for rapid chip fabrication using commercially available thin-film materials such as Mylar, propylene and Kapton are also detailed. Rules of thumb are provided to tune the nucleation and crystal growth to meet users' needs while minimizing sample consumption. These designs provide a reliable approach to forming large crystals and maintaining their hydration for weeks and even months. This allows ample time to grow, select and preserve the best crystal batches before X-ray beam time. Importantly, the fixed-target microfluidic chip has a low background scatter and can be directly used at beamlines without any crystal handling, enabling crystal quality to be preserved. The approach is demonstrated with serial diffraction of photoactive yellow protein, yielding 1.32 Å resolution at room temperature. Fabrication of this standard microfluidic chip with commercially available thin films greatly simplifies fabrication and provides enhanced stability under vacuum. These advances will further broaden microfluidic fixed-target utilization by crystallographers.
Liu, Zhongrui↗
Physical Testing of The PSEC5 ASIC
The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.
Fahey, Alexander [Unlisted, US]↗
The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade
The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.
Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗
Automating Testing of DUNE Electronics via a Finite State Machine
The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six total institutions performing testing. The outcomes of this internship contribute to Fermilab s mission to advance high-energy physics and support the DOE s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.
Kang, Caleb [William Rainey Harper Coll.]↗
Performance of the AstroPix Prototype Module for the Barrel Imaging Calorimeter at the ePIC Detector and in Space-Based Payloads
AstroPix is a high-voltage CMOS (HV-CMOS) monolithic active pixel sensor originally developed to enable precision gamma-ray imaging and spectroscopy in the medium-energy regime (~100 keV–100 MeV) based on the groundwork laid by ATLASpix and MuPix. It features a 500 μm pixel pitch, in-pixel amplification and digitization, and low power consumption (~3-4 mW/cm2), making it scalable for large-area, multilayer telescope detector planes. The detectors have a designed dynamic range of 25 keV to 700 keV. With these features, AstroPix meets the requirements of future space-based high-energy telescopes and the imaging layers of the Barrel Imaging Calorimeter (BIC) in the Electron-Proton/Ion Collider (ePIC) detector at the future Electron-Ion Collider (EIC). For the space-based payload, AstroPix is being integrated into sounding rocket and balloon payloads to demonstrate the technical readiness of the devices. For BIC, AstroPix-based imaging layers interleaved within the lead/scintillating-fiber (Pb/SciFi) sampling calorimeter provide granular shower imaging, enabling key performance features such as electron/pion or gamma/neutral pion separation. As part of the ongoing detector R&D efforts, we have been testing various AstroPix_v3 configurations: the single chip, a quad-chip assembly, a three-layer stack of quad chips, and a 9-chip module that represents the smallest prototype unit of the BIC imaging layer. This presentation will highlight recent performance test results from these AstroPix detector configurations.
Kim, Bobae (ORCID:0000000295396815)↗
Fine-Grained Power and Energy Attribution on AMD GPU/APU-Based Exascale Nodes
Modern exascale GPU- and APU-based systems provide multiple power and energy sensors, but differences in scope, update rate, timing, and filtering complicate the attribution of short-lived accelerator activity. This paper presents a methodology to characterize and correct these effects on Cray EX systems with AMD Instinct MI250X GPUs (Frontier) and MI300A APUs (Portage). Using controlled square-wave workloads, we quantify update intervals, delay, aliasing, and variability across up to 512 GPUs and 480 APUs with on-chip (rocm-smi/amd-smi) and off-chip Cray Power Management sensors. We reconstruct power from cumulative energy counters to achieve faster response times, validate it against on-chip, off-chip, and node-level sensors, and integrate the resulting streams into a Score-P/PAPI-based tool for time-aligned, phase-level attribution. Applied to rocHPL, rocHPL-MxP, and HPG-MxP, the method separates energy savings due to reduced runtime from changes in power. Mixed precision reduces node energy on Frontier by 79% for rocHPL-MxP and 31% for HPG-MxP, with similar trends on Portage. These results provide portable guidance for sensor validation and power-aware optimization on current and future exascale systems.
Mcdaniel, Adam [ORNL] (ORCID:000000016926028X)↗