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At least 91 records · Page 5

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗

Calibration of a compact ASIC-based data acquisition system for neutron/$γ$ discrimination and spectroscopy with organic scintillators

Segmented neutron detectors that use silicon photomultipliers (SiPMs) are receiving significant attention in nuclear security applications. Some of these detectors employ hundreds of channels and would therefore benefit from the use of high-channel-density and low-cost-per-channel data acquisition (DAQ) systems. Candidate DAQ systems that meet these requirements exist, but few perform full waveform digitization, which permits neutron and gamma-ray interaction discrimination via pulse shape. In this work, we study the performance of the TOFPET2 (PETsys Electronics), an ASIC-based DAQ designed for positron emission tomography, which has been adapted to provide sensitivity to pulse shape by the use of variable-period charge integration. We use a light-emitting diode to calibrate a combination of an ON Semiconductor (SensL) 60035-64P J-Series SiPM and TOPFET2 DAQ and evaluate the linearity of their response and dynamic range. Here, the calibration curve was obtained by comparing the DAQ response to that measured with a photodiode interfaced with a traditional waveform digitizer. This calibration process was used for rudimentary spectroscopy of various neutron and sources.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Electrical performances of pre-production staves for the ATLAS ITk Strip Detector Upgrade

The ATLAS experiment is currently preparing for an upgrade of the inner tracking detector for the High-Luminosity LHC. The new tracker, ITk, employs an all-silicon detector with outer strip layers. The building block of the ITk strip barrel is the stave which consists of a low-mass support structure hosting the common electrical, optical and cooling services as well as 28 silicon modules. In this contribution, we outline the challenging aspects of the stave pre-production testing phase at Brookhaven National Laboratory. Here, the electrical characterization of these staves, hosting the final design of all ASICs, will be discussed in detail.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Characterization of LVDS Transmission Data Integrity

Differential Signaling, or LVDS, is a physical layer interface that allows forhigh-speed transmission over short distances, and is an efficient alternative to single-ended signaling. Differential signals are robust to common-mode noise, as the equal and opposite signals both incur identical disturbances. LVDS circuits also utilize a constant current, which allows for lower power consumption. LVDS links will be implemented in future neutrino experiments, so developing and testing a proper design is necessary for incoming projects. This presentation will detail the results of the testing of an LVDS implementation that was designed by the ASIC department at Fermilab.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Preliminary results from the MAMA detectors for the SOHO mission

Multi-Anode Microchannel Array (MAMA) detector systems are being fabricated and tested for use in the Solar Ultraviolet Measurements of Emitted Radiation (SUMER) and the Ultraviolet Coronagraph Spectrometer (UVCS) instruments on the ESA/NASA Solar and Heliospheric Observatory (SOHO) mission. The SOHO MAMA detector systems have formats of 360 x 1024 pixels and pixel dimensions of 25 x 25 sq microns and are optimized for operation at Extreme Ultraviolet (EUV) wavelengths between 40 and 160 nm. In this paper we report on the initial results of measurements of the performance characteristics of the first flight-configuration detector system employing the new custom Application Specific Integrated Circuits (ASICs) which are designed to improve both the dynamic range and the uniformity of response. The performance characteristics of this detector system are compared with those of earlier breadboard systems employing discrete-component electronics circuits.

Slater, David C.↗

Mobile Sensor Technologies Being Developed

The NASA Glenn Research Center is developing small mobile platforms for sensor placement, as well as methods for communicating between roving platforms and a central command location. The first part of this project is to use commercially available equipment to miniaturize an existing sensor platform. We developed a five-circuit-board suite, with an average board size of 1.5 by 3 cm. Shown in the preceding photograph, this suite provides all motor control, direction finding, and communications capabilities for a 27- by 21- by 40-mm prototype mobile platform. The second part of the project is to provide communications between mobile platforms, and also between multiple platforms and a central command location. This is accomplished with a low-power network labeled "SPAN," Sensor Platform Area Network, a local area network made up of proximity elements. In practice, these proximity elements are composed of fixed- and mobile-sensor-laden science packages that communicate to each other via radiofrequency links. Data in the network will be shared by a central command location that will pass information into and out of the network through its access to a backbone element. The result will be a protocol portable to general purpose microcontrollers satisfying a host of sensor networking tasks. This network will enter the gap somewhere between television remotes and Bluetooth but, unlike 802.15.4, will not specify a physical layer, thus allowing for many data rates over optical, acoustical, radiofrequency, hardwire, or other media. Since the protocol will exist as portable C-code, developers may be able to embed it in a host of microcontrollers from commercial to space grade and, of course, to design it into ASICs. Unlike in 802.15.4, the nodes will relate to each other as peers. A demonstration of this protocol using the two test bed platforms was recently held. Two NASA modified, commercially available, mobile platforms communicated and shared data with each other and a central command location. Web-based control and interrogation of similar mobile sensor platforms have also been demonstrated. Expected applications of this technology include robotic planetary exploration, astronaut-to-equipment communication, and remote aerospace engine inspections.

FROM↗

A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments

We present the design principle and test results of a data transmitting ASIC, GBS20, for particle physics experiments. The goal of GBS20 will be an ASIC that employs two serializers each from the 10.24 Gbps lpGBT SerDes, sharing the PLL also from lpGBT. A PAM4 encoder plus a VCSEL driver will be implemented in the same die to use the same clock system, eliminating the need of CDRs in the PAM4 encoder. This way the transmitter module, GBT20, developed using the GBS20 ASIC, will have the exact lpGBT data interface and transmission protocol, with an output up to 20.48 Gbps over one fiber. With PAM4 embedded FPGAs at the receiving end, GBT20 will halve the fibers needed in a system and better use the input bandwidth of the FPGA. A prototype, GBS20v0 is fabricated using a commercial 65 nm CMOS technology. This prototype has two serializers and a PAM4 encoder sharing the lpGBT PLL, but no user data input. An internal PRBS generator provides data to the serializers. GBS20v0 is tested barely up to 20.48 Gbps. With lessons learned from this prototype, we are designing the second prototype, GBS20v1, that will have 16 user data input channels each at 1.28 Gbps. We present the design concept of the GBS20 ASIC and the GBT20 module, the preliminary test results, and lessons learned from GBS20v0 and the design of GBS20v1 which will be not only a test chip but also a user chip with 16 input data channels.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Divalent cation and chloride ion sites of chicken acid sensing ion channel 1a elucidated by x-ray crystallography

Acid sensing ion channels (ASICs) are proton-gated ion channels that are members of the degenerin/epithelial sodium channel superfamily and are expressed throughout central and peripheral nervous systems. ASICs have been implicated in multiple physiological processes and are subject to numerous forms of endogenous and exogenous regulation that include modulation by Ca 2+ and Cl - ions. However, the mapping of ion binding sites as well as a structure-based understanding of the mechanisms underlying ionic modulation of ASICs have remained elusive. Here we present ion binding sites of chicken ASIC1a in resting and desensitized states at high and low pH, respectively, determined by anomalous diffraction x-ray crystallography. The acidic pocket serves as a nexus for divalent cation binding at both low and high pH, while we observe divalent cation binding within the central vestibule on the resting channel at high pH only. Moreover, neutralization of residues positioned to coordinate divalent cations via individual and combined Glu to Gln substitutions reduced, but did not extinguish, modulation of proton-dependent gating by Ca 2+ . Additionally, we demonstrate that anion binding at the canonical thumb domain site is state-dependent and present a previously undetected anion site at the mouth of the extracellular fenestrations on the resting channel. Our results map anion and cation sites on ASICs across multiple functional states, informing possible mechanisms of modulation and providing a blueprint for the design of therapeutics targeting ASICs.

59 BASIC BIOLOGICAL SCIENCES↗

Setup and Testing of PSEC5 ASIC Boards

The PSEC5 ASIC is a high-speed waveform sampling chip developed for precise measurements. This report presents the design review, test board configurations, and results from functional validation of the PSEC5 device. Key aspects examined include power integrity, voltage-controlled oscillator (VCO) behavior, SPI register functionality, clock division characteristics, readout performance, and analog biasing response. Tests were conducted across two boards under varied voltage conditions and signal configurations. Notable observations include robust VCO output, SPI communication irregularities, and anomalous readout conditions. The findings support design iterations for improved ASIC operability and firmware integration.

Fahey, Alexander [North Central Coll.]↗

A Low-Power Correlator ASIC for Arrays with Many Antennas

We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

radio telescopes↗

A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 2$^{7}$-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

The AMACStar ASIC for the HL-LHC ATLAS ITk Strip detector: design, verification, testing, and quality assurance

For the high-luminosity upgrade to the LHC (HL-LHC), the ATLAS detector at CERN requires an all-new inner detector, the Inner Tracker (ITk). The ITk Strip subdetector is made up of silicon modules, which include three types of radiation-hard ASICs. One of these is the Autonomous Monitor and Control (AMAC). The AMAC is manufactured by Global Foundries using 130 nm CMOS8RF DM technology and is approximately 3 by 5 mm in size. This ASIC autonomously monitors the temperatures, voltages, and currents in the module components while controlling critical values in order to prevent these quantities from reaching dangerous levels. The final design, AMACStar, was verified, tested, and ensured to perform all necessary functions. A quality control procedure using an in-house probe station set-up was developed in order to ensure that every individual chip on each wafer of AMACStars required by the ITk Strip project met performance requirements. The average per wafer yield of usable AMACStars is 92.33%, exceeding the design-specific 90% yield estimated for project costing. This estimate was based on actual yields for similar designs in this process.

Analogue electronic circuits↗

A High-Density GaAs Gate Array Chip Set for a Deep Space Digital Receiver

The Jet Propulsin Laboratory (JPL), a division of the California Institute of Technology, performs research, development, and related activities for the National Aeronautics and Space Administration (NASA). JPL is NASA's lead center for unmanned exploration of the solar system and beyond.

designing the ASIC's chip set static timing analyz↗

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

FOS: Computer and information sciences↗

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

Schulte, Jan-Frederik [Purdue U.] (ORCID:000000034↗

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments

We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gbps (DLAS10) and three Miniature Optical Transmitter/Receiver/Transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two Transmitter Optical Sub-Assemblies (TOSAs) of Vertical Cavity Surface Emitting Lasers (VCSELs), receive the signals from two Receiver Optical Sub-Assemblies (ROSAs) that have no embedded limiting amplifiers, or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input Continuous Time Linear Equalizer (CTLE), a four-stage limiting amplifier (LA), and an output driver. The LA amplifies the signals of variable levels to a stable swing. The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65 nm CMOS technology. The die is 1 mm x 1 mm. DLAS10 is packaged in a 4 mm x 4 mm 24-pin quad-flat no-leads (QFN) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10 Gbps eye mask test. Furthermore, the input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (RMS) and a deterministic jitter of 9.9 ps. Each MTx+/MTRx+ module consumes 82 mW/ch and 174 mW/ch, respectively.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗