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All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Processing techniques for software based SAR processors

Software SAR processing techniques defined to treat Shuttle Imaging Radar-B (SIR-B) data are reviewed. The algorithms are devised for the data processing procedure selection, SAR correlation function implementation, multiple array processors utilization, cornerturning, variable reference length azimuth processing, and range migration handling. The Interim Digital Processor (IDP) originally implemented for handling Seasat SAR data has been adapted for the SIR-B, and offers a resolution of 100 km using a processing procedure based on the Fast Fourier Transformation fast correlation approach. Peculiarities of the Seasat SAR data processing requirements are reviewed, along with modifications introduced for the SIR-B. An Advanced Digital SAR Processor (ADSP) is under development for use with the SIR-B in the 1986 time frame as an upgrade for the IDP, which will be in service in 1984-5.

Leung, K.↗
NASA NTRS1983

Performance evaluation of the JPL interim digital SAR processor

The performance of the Interim Digital SAR Processor (IDP) was evaluated. The IDP processor was originally developed for experimental processing of digital SEASAT SAR data. One phase of the system upgrade which features parallel processing in three peripheral array processors, automated estimation for Doppler parameters, and unsupervised image pixel location determination and registration was executed. The method to compensate for the target range curvature effect was improved. A four point interpolation scheme is implemented to replace the nearest neighbor scheme used in the original IDP. The processor still maintains its fast throughput speed. The current performance and capability of the processing modes now available on the IDP system are updated.

Wu, C.↗
NASA NTRS1997

Sequence information signal processor for local and global string comparisons

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Peterson, John C.↗
NASA NTRS1982

A scheme for handling arrays in data-flow systems

An examination of the effects of atomicity (higher resolution) on the performance of array processors (data-flow computers) is presented. Data-flow principles are reviewed, noting the reliance on parallel processing using functional languages to specify sequencing of the operations. Techniques are described for eliminating the necessity of copying whole arrays between processing steps, thereby reducing the number of store cycles. The method involves setting whole columns to specific values rather than individual elements. The individual column values can be processed in parallel, i.e., a locally optimized condition exists. A drawback of the system is the need for more low level arguments, to identify the appropriate processing sequences, and high system complexity.

Gaudiot, J.-L.↗
NASA NTRS1988

The U.S. Sarsat geosynchronous experiment - Ground processor description and test results

The development of a specialized digital signal processor, the Geosynchronous Signal Processor (GSP), for short beacon burst signal detection and demodulation is described. The processing is based on fast Fourier Transform techniques for detection and message integration on the respective message bursts for demodulation. The GSP is based on array processor technology; it is designed to yield an ultimate capacity of 50-75 simultaneous beacon transmissions within the nominal 20 KHz bandwidth centered at 406.025 MHz.

Flikkema, P. G.↗
NASA NTRS1984

Goldstone R/D High Speed Data Acquisition System

A digital data acquisition system that meets the requirements of several users (initially the planetary radar program) is planned for general use at Deep Space Station 14 (DSS 14). The system, now partially complete, is controlled by VAX 11/780 computer that is programmed in high level languages. A DEC Data Controller is included for moderate-speed data acquisition, low speed data display, and for a digital interface to special user-provided devices. The high-speed data acquisition is performed in devices that are being designed and built at JPL. Analog IF signals are converted to a digitized 50 MHz real signal. This signal is filtered and mixed digitally to baseband after which its phase code (a PN sequence in the case of planetary radar) is removed. It may then be accumulated (or averaged) and fed into the VAX through an FPS 5210 array processor. Further data processing before entering the VAX is thus possible (computation and accumulation of the power spectra, for example). The system is to be located in the research and development pedestal at DSS 14 for easy access by researchers in radio astronomy as well as telemetry processing and antenna arraying.

Deutsch, L. J.↗
NASA NTRS1983

Parallel architectures for iterative methods on adaptive, block structured grids

A parallel computer architecture well suited to the solution of partial differential equations in complicated geometries is proposed. Algorithms for partial differential equations contain a great deal of parallelism. But this parallelism can be difficult to exploit, particularly on complex problems. One approach to extraction of this parallelism is the use of special purpose architectures tuned to a given problem class. The architecture proposed here is tuned to boundary value problems on complex domains. An adaptive elliptic algorithm which maps effectively onto the proposed architecture is considered in detail. Two levels of parallelism are exploited by the proposed architecture. First, by making use of the freedom one has in grid generation, one can construct grids which are locally regular, permitting a one to one mapping of grids to systolic style processor arrays, at least over small regions. All local parallelism can be extracted by this approach. Second, though there may be a regular global structure to the grids constructed, there will be parallelism at this level. One approach to finding and exploiting this parallelism is to use an architecture having a number of processor clusters connected by a switching network. The use of such a network creates a highly flexible architecture which automatically configures to the problem being solved.

Gannon, D.↗
NASA NTRS1986

ERS-1 SAR data processing

To take full advantage of the synthetic aperature radar (SAR) to be flown on board the European Space Agency's Remote Sensing Satellite (ERS-1) (1989) and the Canadian Radarsat (1990), the implementation of a receiving station in Alaska is being studied to gather and process SAR data pertaining in particular to regions within the station's range of reception. The current SAR data processing requirement is estimated to be on the order of 5 minutes per day. The Interim Digital Sar Processor (IDP) which was under continual development through Seasat (1978) and SIR-B (1984) can process slightly more than 2 minutes of ERS-1 data per day. On the other hand, the Advanced Digital SAR Processore (ADSP), currently under development for the Shuttle Imaging Radar C (SIR-C, 1988) and the Venus Radar Mapper, (VMR, 1988), is capable of processing ERS-1 SAR data at a real time rate. To better suit the anticipated ERS-1 SAR data processing requirement, both a modified IDP and an ADSP derivative are being examined. For the modified IDP, a pipelined architecture is proposed for the mini-computer plus array processor arrangement to improve throughout. For the ADSP derivative, a simplified version is proposed to enhance ease of implementation and maintainability while maintaing real time throughput rates. These processing systems are discussed and evaluated.

Leung, K.↗
NASA NTRS1989

A vector scanning processing technique for pulsed laser velocimetry

Pulsed-laser-sheet velocimetry yields two-dimensional velocity vectors across an extended planar region of a flow. Current processing techniques offer high-precision (1-percent) velocity estimates, but can require hours of processing time on specialized array processors. Sometimes, however, a less accurate (about 5 percent) data-reduction technique which also gives unambiguous velocity vector information is acceptable. Here, a direct space-domain processing technique is described and shown to be far superior to previous methods in achieving these objectives. It uses a novel data coding and reduction technique and has no 180-deg directional ambiguity. A complex convection vortex flow was recorded and completely processed in under 2 min on an 80386-based PC, producing a two-dimensional velocity-vector map of the flowfield. Pulsed-laser velocimetry data can thus be reduced quickly and reasonably accurately, without specialized array processing hardware.

Wernet, Mark P.↗
NASA NTRS1989

A vector scanning processing technique for pulsed laser velocimetry

Pulsed laser sheet velocimetry yields nonintrusive measurements of two-dimensional velocity vectors across an extended planar region of a flow. Current processing techniques offer high precision (1 pct) velocity estimates, but can require several hours of processing time on specialized array processors. Under some circumstances, a simple, fast, less accurate (approx. 5 pct), data reduction technique which also gives unambiguous velocity vector information is acceptable. A direct space domain processing technique was examined. The direct space domain processing technique was found to be far superior to any other techniques known, in achieving the objectives listed above. It employs a new data coding and reduction technique, where the particle time history information is used directly. Further, it has no 180 deg directional ambiguity. A complex convection vortex flow was recorded and completely processed in under 2 minutes on an 80386 based PC, producing a 2-D velocity vector map of the flow field. Hence, using this new space domain vector scanning (VS) technique, pulsed laser velocimetry data can be reduced quickly and reasonably accurately, without specialized array processing hardware.

Wernet, Mark P.↗
NASA NTRS1987

Rectification of terrain induced distortions in radar imagery

This paper describes a technique to generate geocoded synthetic aperture radar (SAR) imagery corrected for terrain induced geometric distortions. This algorithm transforms the raw slant range image, generated by the signal processor, into a map registered product, resampled to either Universal Transverse Mercator (UTM) or Polar Stereographic projections, and corrected for foreshortening. The technique utilizes the space platform trajectory information in conjunction with a digital elevation map (DEM) of the target area to generate an ortho-radar map with near-autonomous operation. The current procedure requires only two to three tie-points to compensate for the platform position uncertainty that results in translational error between the image and the DEM. This approach is unique in that it does not require generation of a simulated radar image from the DEM or a grid of tie-points to characterize the image-to-map distortions. Rather, it models the inherent distortions based on knowledge of the radar data collection characteristics, the signal Doppler parameters, and the local terrain height to automatically predict the registration transformation. This algorithm has been implemented on a minicomputer system equipped with an array processor and a large random-access memory to optimize the throughput.

Kwok, Ronald↗
NASA NTRS1995

Prototype Focal-Plane-Array Optoelectronic Image Processor

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

Fang, Wai-Chi↗
DOE OSTI2022

Performance of the ATLAS Level-1 topological trigger in Run 2

During LHC Run 2 (2015–2018) the ATLAS Level-1 topological trigger allowed efficient data-taking by the ATLAS experiment at luminosities up to 2.1x10 34 cm -2 s -1 , which exceeds the design value by a factor of two. The system was installed in 2016 and operated in 2017 and 2018. It uses Field Programmable Gate Array processors to select interesting events by placing kinematic and angular requirements on electromagnetic clusters, jets, τ-leptons, muons and the missing transverse energy. It allowed to significantly improve the background event rejection and signal event acceptance, in particular for Higgs and B-physics processes.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1978

Data Management Symposium, Huntsville, Ala., October 18, 19, 1977, Proceedings

The transfer, processing, and use of satellite data are discussed. Topics relating to simulation and processing techniques include computer design assessments through simulation, data system dynamic simulation, and future timing accuracy requirements and procedures for data processing. Subjects relevant to data base management systems and users and their needs include an image-based information system architecture for correlation satellite and topological data base, efficient searching and sorting applications using an associative array processor, analysis of user's needs for a large technical data base, and variable length data formats. The technology development outlook was considered with attention to data systems technology outlook for supporting NASA programs, a user-oriented interactive information extraction system, and flow control and sorting techniques for telemetry packets.

Castelli, A.↗
NASA NTRS1978

Variable length data formats

The purpose of this paper is to discuss a number of variable length floating point and integer formats and to give the various advantages and disadvantages of their use. Often it is known in advance that a given integer will not exceed a certain magnitude or that a particular floating point number is accurate to only 'n' places of accuracy. Faced with this, it is good engineering to choose variable length floating point and integer formats which require the least amount of hardware or the minimum amount of software or which have some other dominant advantage. The formats discussed have the advantage that length change algorithms are invariant with respect to data types (unsigned, signed, floating point, integers, and complex numbers). The STARAN associative array processor, which uses a completely variable fixed point and floating point formats, is described.

Brakefield, J. C.↗
NASA NTRS1979

The suitability of the ILLIAC IV architecture for image processing

The major architectural features of the ILLIAC IV large scale, array processor are summarized along with their applicability to image processing. Several image processing algorithms are considered, including multispectral classification, texture feature extraction, two-dimensional Fourier transform, and synthetic aperture radar processing. The basic parallelism of the ILLIAC IV (64 processing elements acting in lock-step) is usually fully utilized by the image processing applications. The major architectural aspect of the system with respect to image processing is the relatively small local scratch-pad memory and the long latency time to access the main storage device. The major precision used for the image processing applications is the 32-bit floating point, given a choice of 8-bit integers and 64-bit floating point.

Stevenson, D. K.↗