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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 883 records · Page 49
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

PEGASUS 5: An Automated Pre-Processor for Overset-Grid CFD

An all new, automated version of the PEGASUS software has been developed and tested. PEGASUS provides the hole-cutting and connectivity information between overlapping grids, and is used as the final part of the grid generation process for overset-grid computational fluid dynamics approaches. The new PEGASUS code (Version 5) has many new features: automated hole cutting; a projection scheme for fixing gaps in overset surfaces; more efficient interpolation search methods using an alternating digital tree; hole-size optimization based on adding additional layers of fringe points; and an automatic restart capability. The new code has also been parallelized using the Message Passing Interface standard. The parallelization performance provides efficient speed-up of the execution time by an order of magnitude, and up to a factor of 30 for very large problems. The results of three example cases are presented: a three-element high-lift airfoil, a generic business jet configuration, and a complete Boeing 777-200 aircraft in a high-lift landing configuration. Comparisons of the computed flow fields for the airfoil and 777 test cases between the old and new versions of the PEGASUS codes show excellent agreement with each other and with experimental results.

Suhs, Norman E.↗
NASA NTRS1989

Image Processor

Texas Instruments Programmable Remapper is a research tool used to determine how to best utilize the part of a patient's visual field still usable by mapping onto his field of vision with manipulated imagery. It is an offshoot of a NASA program for speeding up, improving the accuracy of pattern recognition in video imagery. The Remapper enables an image to be "pushed around" so more of it falls into the functional portions in the retina of a low vision person. It works at video rates, and researchers hope to significantly reduce its size and cost, creating a wearable prosthesis for visually impaired people.

Source record↗
NASA NTRS2003

Chapman-1024 Processor Shared Memory

NASA has developed new technology that improves upon weakness in current mainstream supercomputer designs: those of "scalability," "humadmachine interface," and "load balancing." The system simplifies running large computer simulations of national and international importance like climate prediction and space vehicle design.

Ciotii, Robert↗
NASA NTRS2002

X2000 advanced avionics characterization study : Living in the modern world of difficult to predict processor performance

The characterization study has shown that adjustments in an application's data accesses can easily create a performance difference of three or more times in actual applications. In general, by iterating over a small portion of a data set rather than its entirety, execution can remain within cache thereby producing a performance increase. Additionally, the approaches used in performing I/O can make a major performance difference.

X2000 advanced avionics project↗
NASA NTRS2002

Processor in memory

Explore the source record for details and available documents.

HTMT memory PIM↗
NASA NTRS1997

ASF RADARSAT Processor System Performance Summary

The Alaska SAR Facility (ASF) located at the University of Alaska Fairbanks (UAF) has been in operations since 1991 serving as a key data acquisition, processing, archive and distribution center for a number of polar orbiting SAR (synthetic aperture radar) satelittes including ERS 1/2 and JERS-1.

synthetic aperture radar RADARSAT Mapping↗
NASA NTRS1996

(abstract) A High Throughput 3-D Inner Product Processor

A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated.

imaging parallel processing algorithms linear vect↗
NASA NTRS1997

64x64 Analog Input Array for 3-Dimensional Neural Network Processor

In pattern recognition and classification for spatio-temporal problems, one of the most challenging tasks is to provide a good and valid solution in real-time. Because of time constraints, software-based neural network approaches may not be suitable for practical use. Hardware solutions seem to be good candidates for this class of problems. Currently, the Three Dimensional Analog Neural Network (3-DANN) is an effective approach to solving spatio-temporal problems in three-dimensional hardware.

spatio-temporal 3-DANN Three Dimensional Analog Ne↗