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Optimizing frequency allocation for fixed-frequency superconducting quantum processors
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Quantum Information Scrambling on a Superconducting Qutrit Processor
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Randomized Compiling for Scalable Quantum Computing on a Noisy Superconducting Quantum Processor
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Midcircuit Measurements on a Single-Species Neutral Alkali Atom Quantum Processor
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Computation of Molecular Spectra on a Quantum Processor with an Error-Resilient Algorithm
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Qubit-ADAPT-VQE: An Adaptive Algorithm for Constructing Hardware-Efficient Ansätze on a Quantum Processor
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Holographic Simulation of Correlated Electrons on a Trapped-Ion Quantum Processor
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Blueprint for a High-Performance Fluxonium Quantum Processor
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Simulating Models of Challenging Correlated Molecules and Materials on the Sycamore Quantum Processor
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Shadow Distillation: Quantum Error Mitigation with Classical Shadows for Near-Term Quantum Processors
Mitigating errors in quantum information processing devices is especially important in the absence of fault tolerance. An effective method in suppressing state-preparation errors is using multiple copies to distill the ideal component from a noisy quantum state. Here, we use classical shadows and randomized measurements to circumvent the need for coherent access to multiple copies at an exponential cost. We study the scaling of resources using numerical simulations and find that the overhead is still favorable compared to full state tomography. We optimize measurement resources under realistic experimental constraints and apply our method to an experiment preparing a Greenberger-Horne-Zeilinger state with trapped ions. In addition to improving stabilizer measurements, the analysis of the improved results reveals the nature of errors affecting the experiment. Hence, our results provide a directly applicable method for mitigating errors in near-term quantum computers.
Deterministic Constant-Depth Preparation of the AKLT State on a Quantum Processor Using Fusion Measurements
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Distributed Application Architecture and LinkNet Topology Processor for Distribution Networks Using the Common Information Model
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Processing-in-Memory Enabled Graphics Processors for 3D Rendering
The performance of 3D rendering of Graphics Processing Unit that convents 3D vector stream into 2D frame with 3D image effects significantly impact users’ gaming experience on modern computer systems. Due to the high texture throughput in 3D rendering, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D stacked memory systems such as Hybrid Memory Cube (HMC) provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Based on the observation that texel fetches significantly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPU for efficient 3D rendering.
Memory System Design for Ultra Low Power Computationally Error Resilient Processor Microarchitectures.
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Evaluating the Intel Skylake Xeon Processor for HPC Workloads.
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Modular Spiking Neural Circuits for Mapping Long Short-Term Memory on a Neurosynaptic Processor
Due to the distributed and asynchronous nature of neural computation through low-energy spikes, brain-inspired hardware systems offer high energy efficiency and massive parallelism. One such platform is the IBM TrueNorth neurosynaptic system. Recently, TrueNorth compatible representation learning algorithms have emerged, achieving close to the state-of-the-art performance in various data sets. However, its application in temporal sequence processing models, such as recurrent neural networks (RNNs), is still only at the proof of concept level. There is an inherent difficulty in capturing temporal dynamics of an RNN using spiking neurons, which is only exasperated by the hardware constraints in connectivity and synaptic weight resolution. This paper presents a design flow that overcomes these difficulties and maps a special case of recurrent networks called long short-term memory (LSTM) onto a spike-based platform. The framework utilizes various approximation techniques, such as activation discretization, weight quantization, and scaling and rounding, spiking neural circuits that implement the complex gating mechanisms, and a store-and-release technique to enable neuron synchronization and faithful storage. While the presented techniques can be applied to map LSTM to any spiking neural network (SNN) simulator/emulator, here we choose the TrueNorth chip as the target platform by adhering to its hardware constraints. Three LSTM applications, parity check, extended Reber grammar, and question classification, are evaluated. The tradeoffs among accuracy, performance, and energy tradeoffs achieved on TrueNorth are demonstrated. Finally, this is compared with the performance on an SNN platform without hardware constraints, which represents the upper bound of the achievable accuracy.