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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 883 records · Page 49
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Programmable Direct-Memory-Access Controller

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Hendry, David F.↗
NASA NTRS1991

Single board system for fuzzy inference

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Symon, James R.↗
NASA NTRS1980

TIROS-N Cosmic Ray study

An experimental and analytical study was performed on the impact of galactic cosmic rays on the TIROS-N satellite memory in orbit. Comparisons were made of systems equipped with the Harris HMI-6508 1 x 1024 CMOS/bulk RAM and the RCA CDP-1821 1 x 1024 bit CMOS/SOS RAM. Based upon the experimental results, estimated bit error rates were determined. These were at least 8.0 bit errors/day for a 300 kilobit memory with the HMI-6508 and .014 bit errors/day with the CDF-1821. It was also estimated that the HMI-6508 latchup rate in orbit is at least two orders of magnitude less than the bit error rates; the CDP-1821 will not latchup.

Blandford, J. T., Jr.↗
DOE OSTI2024

IRIS-GNN: Leveraging Graph Neural Networks for Scheduling on Truly Heterogeneous Runtime Systems

The diversity of accelerators in computer systems poses significant challenges for software developers, such as managing vendor-specific compiler toolchains, code fragmentation requiring different kernel implementations, and performance portability issues. To address these, the Intelligent Runtime System (IRIS) was developed. IRIS works across various systems, from smartphones to supercomputers, enabling automatic performance scaling based on available accelerators. It introduces abstract tasks for seamless execution transitions between accelerators while ensuring memory consistency and task dependencies. Although IRIS simplifies system details, optimal dynamic scheduling still requires user input to understand workload structures. To address this, we introduce a new scheduling policy for IRIS, termed IRIS-GNN, which is the first IRIS hybrid policy that operates in conjunction with the dynamic policies. This policy employs a Graph-Neural Network (GNN) to conduct Graph Classification of any task graphs submitted to IRIS. This GNN analyzes the structure and attributes of the task graph, categorizing it as either locality, concurrency, or mixed. This classification subsequently guides the selection of the dynamic policy used by IRIS. We provide a comparison of the performance of IRIS-GNN against the complete spectrum of IRIS’s dynamic policies, assess the overhead introduced by the GNN within this scheduling framework, and ultimately explore its practical application in real-world scenarios.

Johnston, Beau↗
NASA NTRS1992

Advanced information processing system: Fault injection study and results

The objective of the AIPS program is to achieve a validated fault tolerant distributed computer system. The goals of the AIPS fault injection study were: (1) to present the fault injection study components addressing the AIPS validation objective; (2) to obtain feedback for fault removal from the design implementation; (3) to obtain statistical data regarding fault detection, isolation, and reconfiguration responses; and (4) to obtain data regarding the effects of faults on system performance. The parameters are described that must be varied to create a comprehensive set of fault injection tests, the subset of test cases selected, the test case measurements, and the test case execution. Both pin level hardware faults using a hardware fault injector and software injected memory mutations were used to test the system. An overview is provided of the hardware fault injector and the associated software used to carry out the experiments. Detailed specifications are given of fault and test results for the I/O Network and the AIPS Fault Tolerant Processor, respectively. The results are summarized and conclusions are given.

Burkhardt, Laura F.↗
DOE OSTI2025

Microstructure-sensitive mechanical behavior of an additively manufactured psuedoelastic shape memory alloy

The additive manufacturing of shape memory alloys into complex geometries enables fabrication of advanced functional systems across a variety of fields and domains. This work presents results focused on the mechanical behavior of additively manufactured shape memory pseudoelastic NiTi. The deformation induced solid state phase transformation from austenite to martensite allows this system to accommodate large recoverable strains. This deformation behavior is fundamentally driven by crystal-scale transformation physics. Laser powder bed fusion processing reveals that the resulting microstructure, both grain morphology and crystallographic texture, is strongly dependent on the manufacturing processing history. Exhaustive mechanical testing demonstrates that these microstructural factors strongly impact both tensile and cyclic stress–strain behavior. Cyclic dissipative behavior, however, is similar across all tested microstructures following an initial transient period. Remarkably, analysis of spatial strain fields during tensile loading reveals two distinctly different localization “modes”. The first is initiation of localized deformation bands which continuously propagate through the tensile bar during loading. In the second mode localization is observed but lacks propagation; instead additional localization cites nucleate during subsequent loading. The latter phenomena is suspected to be driven by grain-scale deformation physics as the localized band morphologies coincide with grain morphologies. These phenomena strongly impact the resulting aggregate stress–strain behavior. Hence, manufacturers and designers of psuedoelastic functional components must at the very least consider the potential variability in properties when considering additive manufacturing processing. More ideally the process–structure–property relations can be used to further tailor and optimize final functional performance.

Additive manufacturing↗
NASA NTRS1973

Low cost automated precise time measurement system

The Aerospace Guidance and Metrology Center (AGMC) has the responsibility for the dissemination of Precise Time and Time Interval (PTTI) to Air Force timing systems requiring microsecond time. In order to maintain traceability to the USNO Master Clock in Washington D.C., and accomplish efficient logging of time and frequency data on individual precision clocks, a simple automatic means of acquiring precise time has been devised. The Automatic Time Interval Measurement System (ATIMS) consists of a minicomputer (8K Memory), teletype terminal, electronic counter, Loran C receiver, time base generator and locally-manufactured relay matrix panel. During the measurement process, the computer controls the relay matrix which selects for comparison 13 atomic clocks against a reference clock and the reference versus Loran C. Through use of the system teletype, the operator is able to set the system clock (hours, minutes and seconds), examine and/or modify all clock data and constants, and set measurement intervals. This is done in a conversational manner. A logic flow diagram, system schematic, source listing and software components are included in the presentation.

Alpert, A.↗
NASA NTRS1983

Digital Instrumentation Analysis and Navigation System (DIANS) for system identification

Hardware, software, and performance features of the Digital Instrumentation and Navigation System (DIANS) designed for NASA research to collect flight data as a strap-down system are detailed. The support software for the system has a cross compiler, a linkage editor, and cross assembler, extended communication capabilities, postflight processing applications, and compilers for PASCAL, FORTRAN, CBASIC and MT. The DIANS microcomputer has a 1 Mbyte RAM module, a fast floating point processor board, a 68000 monoboard computer with 64 RAM, a 128 Kbyte bubble memory card, and a navigation radio. The system also carries a battery for full system operation for over an hour. The support software is also stored on a host mainframe computer, which has a CP/M operating system. Pitch, roll, and heading data are gathered from the on-board system, and communication is possible between the airborne and ground-based computer.

Smyth, R. K.↗
NASA NTRS1988

Concurrent Image Processing Executive (CIPE)

The design and implementation of a Concurrent Image Processing Executive (CIPE), which is intended to become the support system software for a prototype high performance science analysis workstation are discussed. The target machine for this software is a JPL/Caltech Mark IIIfp Hypercube hosted by either a MASSCOMP 5600 or a Sun-3, Sun-4 workstation; however, the design will accommodate other concurrent machines of similar architecture, i.e., local memory, multiple-instruction-multiple-data (MIMD) machines. The CIPE system provides both a multimode user interface and an applications programmer interface, and has been designed around four loosely coupled modules; (1) user interface, (2) host-resident executive, (3) hypercube-resident executive, and (4) application functions. The loose coupling between modules allows modification of a particular module without significantly affecting the other modules in the system. In order to enhance hypercube memory utilization and to allow expansion of image processing capabilities, a specialized program management method, incremental loading, was devised. To minimize data transfer between host and hypercube a data management method which distributes, redistributes, and tracks data set information was implemented.

Lee, Meemong↗
NASA NTRS1990

Concurrent Image Processing Executive (CIPE). Volume 1: Design overview

The design and implementation of a Concurrent Image Processing Executive (CIPE), which is intended to become the support system software for a prototype high performance science analysis workstation are described. The target machine for this software is a JPL/Caltech Mark 3fp Hypercube hosted by either a MASSCOMP 5600 or a Sun-3, Sun-4 workstation; however, the design will accommodate other concurrent machines of similar architecture, i.e., local memory, multiple-instruction-multiple-data (MIMD) machines. The CIPE system provides both a multimode user interface and an applications programmer interface, and has been designed around four loosely coupled modules: user interface, host-resident executive, hypercube-resident executive, and application functions. The loose coupling between modules allows modification of a particular module without significantly affecting the other modules in the system. In order to enhance hypercube memory utilization and to allow expansion of image processing capabilities, a specialized program management method, incremental loading, was devised. To minimize data transfer between host and hypercube, a data management method which distributes, redistributes, and tracks data set information was implemented. The data management also allows data sharing among application programs. The CIPE software architecture provides a flexible environment for scientific analysis of complex remote sensing image data, such as planetary data and imaging spectrometry, utilizing state-of-the-art concurrent computation capabilities.

Lee, Meemong↗
DOE OSTI2021

Fast and Scalable Sparse Triangular Solver for Multi-GPU Based HPC Architectures

Designing efficient and scalable sparse linear algebra kernels on modern multi-GPU based HPC systems is a daunting task due to significant irregular memory references and workload imbalance across the GPUs. This is particularly the case for \textit{Sparse Triangular Solver (SpTRSV)} which introduces additional two-dimensional computation dependencies among subsequent computation steps. Dependency information is exchanged and shared among GPUs, thus warrant for efficient memory allocation, data partitioning, and workload distribution as well as fine-grained communication and synchronization support. In this work, we demonstrate that directly adopting unified memory can adversely affect the performance of SpTRSV on multi-GPU architectures, despite linking via fast interconnect like NVLinks and NVSwitches. Alternatively, we employ the latest NVSHMEM technology based on Partitioned Global Address Space programming model to enable efficient fine-grained communication and drastic synchronization overhead reduction. Furthermore, to handle workload imbalance, we propose a malleable task-pool execution model which can further enhance the utilization of GPUs. By applying these techniques, our experiments on the NVIDIA multi-GPU supernode V100-DGX-1 and DGX-2 systems demonstrate that our design can achieve on average 3.53x (up to 9.86x) speedup on a DGX-1 system and 3.66x (up to 9.64x) speedup on a DGX-2 system with 4-GPUs over the Unified-Memory design. The comprehensive sensitivity and scalability studies also show that the proposed zero-copy SpTRSV is able to fully utilize the computing and communication resources of the multi-GPU system.

Xie, Chenhao↗
NASA NTRS1990

Integrating an object system into CLIPS: Language design and implementation issues

This paper describes the reasons why an object system with integrated pattern-matching and object-oriented programming facilities is desirable for CLIPS and how it is possible to integrate such a system into CLIPS while maintaining the run-time performance and the low memory usage for which CLIPS is known. The requirements for an object system in CLIPS that includes object-oriented programming and integrated pattern-matching are discussed and various techniques for optimizing the object system and its integration with the pattern-matcher are presented.

Auburn, Mark↗
NASA NTRS1994

Boundary element analysis on vector and parallel computers

Boundary element analysis (BEA) can be characterized as a numerical technique that generally shifts the computational burden in the analysis toward numerical integration and the solution of nonsymmetric and either dense or blocked sparse systems of algebraic equations. Researchers have explored the concept that the fundamental characteristics of BEA can be exploited to generate effective implementations on vector and parallel computers. In this paper, the results of some of these investigations are discussed. The performance of overall algorithms for BEA on vector supercomputers, massively data parallel single instruction multiple data (SIMD), and relatively fine grained distributed memory multiple instruction multiple data (MIMD) computer systems is described. Some general trends and conclusions are discussed, along with indications of future developments that may prove fruitful in this regard.

Kane, J. H.↗
NASA NTRS2008

Network-Attached Solid-State Recorder Architecture

A document discusses placing memory modules on the high-speed serial interconnect, which is used by a spacecraft s computer elements for inter-processor communications, to allow all multiple computer system architectures to access the spacecraft data storage at the same time. Each memory board is identical electrically and receives its bus ID upon connection to the system. The computer elements are configured in a similar fashion. The architecture allows for multiple memory boards to be accessed simultaneously by different computer elements, and results in a scalable, strong, fault-tolerant system. The IEEE-1393 ring bus can be routed so that multiple card failures can occur and the mass memory storage will still function.

Cox, Brian↗
DOE OSTI2023

Distributed out-of-memory NMF on CPU/GPU architectures

We propose an efficient distributed out-of-memory implementation of the non-negative matrix factorization (NMF) algorithm for heterogeneous high-performance-computing systems. The proposed implementation is based on prior work on NMFk, which can perform automatic model selection and extract latent variables and patterns from data. In this work, we extend NMFk by adding support for dense and sparse matrix operation on multi-node, multi-GPU systems. The resulting algorithm is optimized for out-of-memory problems where the memory required to factorize a given matrix is greater than the available GPU memory. Memory complexity is reduced by batching/tiling strategies, and sparse and dense matrix operations are significantly accelerated with GPU cores (or tensor cores when available). Input/output latency associated with batch copies between host and device is hidden using CUDA streams to overlap data transfers and compute asynchronously, and latency associated with collective communications (both intra-node and inter-node) is reduced using optimized NVIDIA Collective Communication Library (NCCL) based communicators. Benchmark results show significant improvement, from 32X to 76x speedup, with the new implementation using GPUs over the CPU-based NMFk. Good weak scaling was demonstrated on up to 4096 multi-GPU cluster nodes with approximately 25,000 GPUs when decomposing a dense 340 Terabyte-size matrix and an 11 Exabyte-size sparse matrix of density 10 -6 .

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1981

An advanced programmable/reconfigurable color graphics display system for crew station technology research

The hardware configuration, software organization, and applications software for the NASA IKONAS color graphics display system are described. The systems were created at the Langley Research Center Display Device Laboratory to develop, evaluate, and demonstrate advanced generic concepts, technology, and systems integration techniques for electronic crew station systems of future civil aircraft. A minicomputer with 64K core memory acts as a host for a raster scan graphics display generator. The architectures of the hardware system and the graphics display system are provided. The applications software features a FORTRAN-based model of an aircraft, a display system, and the utility program for real-time communications. The model accepts inputs from a two-dimensional joystick and outputs a set of aircraft states. Ongoing and planned work for image segmentation/generation, specialized graphics procedures, and higher level language user interface are discussed.

Montoya, R. J.↗
NASA NTRS1995

Heterogeneous concurrent computing with exportable services

Heterogeneous concurrent computing, based on the traditional process-oriented model, is approaching its functionality and performance limits. An alternative paradigm, based on the concept of services, supporting data driven computation, and built on a lightweight process infrastructure, is proposed to enhance the functional capabilities and the operational efficiency of heterogeneous network-based concurrent computing. TPVM is an experimental prototype system supporting exportable services, thread-based computation, and remote memory operations that is built as an extension of and an enhancement to the PVM concurrent computing system. TPVM offers a significantly different computing paradigm for network-based computing, while maintaining a close resemblance to the conventional PVM model in the interest of compatibility and ease of transition Preliminary experiences have demonstrated that the TPVM framework presents a natural yet powerful concurrent programming interface, while being capable of delivering performance improvements of upto thirty percent.

Sunderam, Vaidy↗
DOE OSTI2023

Independent malware detection architecture

A system and method (referred to as the system) detect malware by training a rule-based model, a functional based model, and a deep learning-based model from a memory snapshot of a malware free operating state of a monitored device. The system extracts a feature set from a second memory snapshot captured from an operating state of the monitored device and processes the feature set by the rule-based model, the functional-based model, and the deep learning-based model. The system identifies identifying instances of malware on the monitored device without processing data identifying an operating system of the monitored device, data associated with a prior identification of the malware, data identifying a source of the malware, data identifying a location of the malware on the monitored device, or any operating system specific data contained within the monitored device.

Smith, Jared M.↗