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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 883 records · Page 49
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Nanomaterials for Electronics and Optoelectronics

Nanomaterials such as carbon nanotubes(CNTs), graphene, and inorganic nanowires(INWs) have shown interesting electronic, mechanical, optical, thermal, and other properties and therefore have been pursued for a variety of applications by the nanotechnology community ranging from electronics to nanocomposites. While the first two are carbon-based materials, the INWs in the literature include silicon, germanium, III-V, II-VI, a variety of oxides, nitrides, antimonides and others. In this talk, first an overview of growth of these three classes of materials by CVD and PECVD will be presented along with results from characterization. Then applications in development of chemical sensors, biosensors, energy storage devices and novel memory architectures will be discussed.

Koehne, Jessica E.↗
NASA NTRS2018

Lessons Learned in the Flight Qualification of the S-NPP and NOAA-20 Solar Array Mechanisms

Deployable solar arrays are the energy source used on almost all Earth orbiting spacecraft and their release and deployment are mission-critical; fully testing them on the ground is a challenging endeavor. The 8 meter long deployable arrays flown on two sequential NASA weather satellites were each comprised of three rigid panels almost 2 meters wide. These large panels were deployed by hinges comprised of stacked constant force springs, eddy current dampers, and were restrained through launch by a set of four releasable hold-downs using shape memory alloy release devices. The ground qualification testing of such unwieldy deployable solar arrays, whose design was optimized for orbital operations, proved to be quite challenging and provides numerous lessons learned. A paperwork review and follow-up inspection after hardware storage determined that there were negative torque margins and missing lubricant, this paper will explain how these unexpected issues were overcome. The paper will also provide details on how the hinge subassemblies, the fully-assembled array, and mechanical ground support equipment were subsequently improved and qualified for a follow-on flight with considerably less difficulty. The solar arrays built by Ball Aerospace Corp. for the Suomi National Polar Partnership (S-NPP) satellite and the Joint Polar Satellite System (JPSS-1) satellite (now NOAA-20) were both successfully deployed on-obit and are performing well.

Helfrich, Daniel↗
NASA NTRS2018

Lessons Learned in the Flight Qualification of the S-NPP and NOAA-20 Solar Array Mechanisms

Deployable solar arrays are the energy source used on almost all Earth orbiting spacecraft and their release and deployment are mission-critical; fully testing them on the ground is a challenging endeavor. The 8 meter long deployable arrays flown on two sequential NASA weather satellites were each comprised of three rigid panels almost 2 meters wide. These large panels were deployed by hinges comprised of stacked constant force springs, eddy current dampers, and were restrained through launch by a set of four releasable hold-downs using shape memory alloy release devices. The ground qualification testing of such unwieldy deployable solar arrays, whose design was optimized for orbital operations, proved to be quite challenging and provides numerous lessons learned. A paperwork review and follow-up inspection after hardware storage determined that there were negative torque margins and missing lubricant, this paper will explain how these unexpected issues were overcome. The paper will also provide details on how the hinge subassemblies, the fully-assembled array, and mechanical ground support equipment were subsequently improved and qualified for a follow-on flight with considerably less difficulty. The solar arrays built by Ball Aerospace Corp. for the Suomi National Polar Partnership (SNPP) satellite and the Joint Polar Satellite System (JPSS-1) satellite (now NOAA-20) were both successfully deployed on-obit and are performing well.

Sexton, Adam↗
DOE OSTI2012

Parallel LU Factorization on GPU cluster

This paper describes our progress in developing software for performing parallel LU factorization of a large dense matrix on a GPU cluster. Three approaches, with increasing software complexity, are considered: (i) a naive 'thunking' approach that links the existing parallel ScaLAPACK software library with cuBLAS through a software emulation layer; (ii) a more intrusive magmaBLAS implementation integrated into the LU solver in the High-Performance Linpack software; and (iii) a left-looking out-of-core algorithm for solving problems that are larger than the available memory on GPU devices. Comparison of the performance gains versus the current ScaLAPACK PZGETRF are provided.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2014

Density-fitted singles and doubles coupled cluster on graphics processing units

We adapt an algorithm for singles and doubles coupled cluster (CCSD) that uses density fitting (DF) or Cholesky decomposition (CD) in the construction and contraction of all electron repulsion integrals (ERI s) for use on heterogeneous compute nodes consisting of a multicore CPU and at least one graphics processing unit (GPU). The use of approximate 3-index ERI s ameliorates two of the major difficulties in designing scientific algorithms for GPU s: (i) the extremely limited global memory on the devices and (ii) the overhead associated with data motion across the PCI bus. For the benzene trimer described by an aug-cc-pVDZ basis set, the use of a single NVIDIA Tesla C2070 (Fermi) GPU accelerates a CD-CCSD computation by a factor of 2.1, relative to the multicore CPU-only algorithm that uses 6 highly efficient Intel core i7-3930K CPU cores. The use of two Fermis provides an acceleration of 2.89, which is comparable to that observed when using a single NVIDIA Kepler K20c GPU (2.73).

Sherrill, David↗
DOE OSTI2020

System and method for controlling an energy beam of an additive manufacturing system

An additive manufacturing system includes an energy beam generator that generates an energy beam to melt and fuse raw materials for a part and a computing device that controls operation of the energy beam generator. The computing device includes a memory element that stores or access a three-dimensional model of the part, and a processing element that receives at least a portion of the three-dimensional model and controls a parameter of the energy beam generator according to a gradient function so as to apply a variable amount of heat to the raw material that forms an overhang on the part.

42 ENGINEERING↗
DOE OSTI2023

Classification based anomaly detection

An example device includes processing circuitry and a memory. The memory includes instructions that cause the device to perform various functions. The functions include receiving datastreams from a plurality of sensors of a high performance computing system, classifying each datastream of the each sensor to one of a plurality of datastream models, selecting an anomaly detection algorithm from a plurality of anomaly detection algorithms for each datastream, determining parameters of the each anomaly detection algorithm, determining an anomaly threshold for each datastream, and generating an indication that the sensor associated with the datastream is acting anomalously.

Serebryakov, Sergey↗
DOE OSTI2025

IRIS-MEMFLOW: Data Flow-Enabled Portable Memory Orchestration in IRIS Runtime for Diverse Heterogeneity

Task-based programming models and execution paradigms provide a means to decompose a computation by expressing it as a graph in which each node represents a specific computation operating on memory objects and the edges define the dependencies in the execution flow. In this execution model, independent nodes in the graph can be executed concurrently in different computing devices, making it suitable for heterogeneous systems in which computing devices with different architectures coexist. However, careful memory orchestration across heterogeneous devices is needed because copies of the same memory object may reside in multiple devices during execution. Manually ensuring such an orchestration is quite challenging. Not only must an application developer guard against race conditions, but they must also optimize data movement between the host and devices because unnecessary data movement significantly impacts performance. To mitigate these challenges, we enhance the IRIS heterogeneous runtime and introduce IRIS-MEMFLOW–a data flow–enabled portable memory abstraction for seamlessly orchestrating memory in diverse heterogeneous computing environments. By using data-flow analysis, IRIS-MEMFLOW guards against race conditions while multiple heterogeneous devices access memory objects. IRIS-MEMFLOW also optimizes data movement between the host and devices without manual intervention. As a result, IRIS provides improved programming productivity, performance, and portability for multidevice heterogeneous executions in high-performance computing and cloud systems that run diverse architectures from different vendors. The efficacy of IRIS-MEMFLOW is evaluated through experiments that show its capability in terms of programming productivity, multidevice heterogeneity, portability, and low overhead versus the state of the art.

Monil, M. A. H. [ORNL] (ORCID:0000000334194037)↗
DOE OSTI2021

A domain wall-magnetic tunnel junction artificial synapse with notched geometry for accurate and efficient training of deep neural networks

Inspired by the parallelism and efficiency of the brain, several candidates for artificial synapse devices have been developed for neuromorphic computing, yet a nonlinear and asymmetric synaptic response curve precludes their use for backpropagation, the foundation of modern supervised learning. Spintronic devices—which benefit from high endurance, low power consumption, low latency, and CMOS compatibility—are a promising technology for memory, and domain-wall magnetic tunnel junction (DW-MTJ) devices have been shown to implement synaptic functions such as long-term potentiation and spike-timing dependent plasticity. In this work, we propose a notched DW-MTJ synapse as a candidate for supervised learning. Using micromagnetic simulations at room temperature, we show that notched synapses ensure the non-volatility of the synaptic weight and allow for highly linear, symmetric, and reproducible weight updates using either spin transfer torque (STT) or spin–orbit torque (SOT) mechanisms of DW propagation. We use lookup tables constructed from micromagnetics simulations to model the training of neural networks built with DW-MTJ synapses on both the MNIST and Fashion-MNIST image classification tasks. Accounting for thermal noise and realistic process variations, the DW-MTJ devices achieve classification accuracy close to ideal floating-point updates using both STT and SOT devices at room temperature and at 400 K. Our work establishes the basis for a magnetic artificial synapse that can eventually lead to hardware neural networks with fully spintronic matrix operations implementing machine learning.

42 ENGINEERING↗
DOE OSTI2019

Redox transistors for neuromorphic computing

Efficiency bottlenecks inherent to conventional computing in executing neural algorithms have spurred the development of novel devices capable of “in-memory” computing. Commonly known as “memristors,” a variety of device concepts including conducting bridge, vacancy filament, phase change, and other types have been proposed as promising elements in artificial neural networks for executing inference and learning algorithms. In this article, we review the recent advances in memristor technology for neuromorphic computing and discuss strategies for addressing the most significant performance challenges, including nonlinearity, high read/write currents, and endurance. As an alternative to two-terminal memristors, we introduce the three-terminal electrochemical memory based on the redox transistor (RT), which uses a gate to tune the redox state of the channel. Decoupling the “read” and “write” operations using a third terminal and storage of information as a charge-compensated redox reaction in the bulk of the transistor enables high-density information storage. These properties enable low-energy operation without compromising analog performance and nonvolatility. Finally, we discuss the RT operating mechanisms using organic and inorganic materials, approaches for array integration, and prospects for achieving the device density and switching speeds necessary to make electrochemical memory competitive with established digital technology.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Superconducting neural networks with disordered Josephson junction array synaptic networks and leaky integrate-and-fire loop neurons

Fully coupled randomly disordered recurrent superconducting networks with additional open-ended channels for inputs and outputs are considered the basis to introduce a new architecture to neuromorphic computing in this work. Various building blocks of such a network are designed around disordered array synaptic networks using superconducting devices and circuits as an example, while emphasizing that a similar architectural approach may be compatible with several other materials and devices. A multiply coupled (interconnected) disordered array of superconducting loops containing Josephson junctions [equivalent to superconducting quantum interference devices (SQUIDs)] forms the aforementioned collective synaptic network that forms a fully recurrent network together with compatible neuron-like elements and feedback loops, enabling unsupervised learning. This approach aims to take advantage of superior power efficiency, propagation speed, and synchronizability of a small world or a random network over an ordered/regular network. Additionally, it offers a significant factor of increase in scalability. Here, a compatible leaky integrate-and-fire neuron made of superconducting loops with Josephson junctions is presented, along with circuit components for feedback loops as needed to complete the recurrent network. Several of these individual disordered array neural networks can further be coupled together in a similarly disordered way to form a hierarchical architecture of recurrent neural networks that is often suggested as similar to a biological brain.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2017

Ferroelectric symmetry-protected multibit memory cell

Here, the tunability of electrical polarization in ferroelectrics is instrumental to their applications in information-storage devices. The existing ferroelectric memory cells are based on the two-level storage capacity with the standard binary logics. However, the latter have reached its fundamental limitations. Here we propose ferroelectric multibit cells (FMBC) utilizing the ability of multiaxial ferroelectric materials to pin the polarization at a sequence of the multistable states. Employing the catastrophe theory principles we show that these states are symmetry-protected against the information loss and thus realize novel topologically-controlled access memory (TAM). Our findings enable developing a platform for the emergent many-valued non-Boolean information technology and target challenges posed by needs of quantum and neuromorphic computing.

36 MATERIALS SCIENCE↗
NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗
DOE OSTI2013

Process for fabricating piezoelectrically actuated ultrananocrystalline diamond tip array integrated with ferroelectric or phase change media for high-density memory

A process for fabricating a piezoactuated storage device having a tip array and a memory media, which includes but is not limited to: etching the regions on the surface of the silicon wafer to produce substantially pyramidal etch pits by anisotropic etching or chemical etching with potassium hydroxide (KOH); growing an oxide layer on a top surface of the silicon wafer and in the substantially pyramidal etch pits to produce oxidation sharpening of the substantially pyramidal etch pits; forming an array of conductive tips of a nanocarbon film of nanostructured carbon material by deposition, wherein the nanostructured carbon material is ultrananocrystalline diamond (UNCD), ta-C, or diamond-like carbon films; and forming an oxygen diffusion barrier layer by deposition of a TiAl, TaAl, or any other oxygen diffusion barrier layer material on the nanocarbon film.

Auciello, Orlando H.↗
DOE OSTI2022

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗
DOE OSTI2018

Atomically Thin CBRAM Enabled by 2-D Materials: Scaling Behaviors and Performance Limits

Reducing the energy and power dissipation of conductive bridge random access memory (CBRAM) cells is of critical importance for their applications in future Internet of Things (IoT) device and neuromorphic computing platforms. Atomically thin CBRAMs enabled by 2-D materials are studied theoretically by using 3-D kinetic Monte Carlo simulations together with experimental characterization. The results indicate the performance potential of attoJoule energy dissipation for intrinsic filament formation and a filament size of a single atomistic chain in such a CBRAM cell. The atomically thin CBRAM cells also show qualitatively different features from conventional CBRAM cells, including complete rupture of the filament in the reset stage and comparable forming and set voltages. The scaling and variability of the CBRAM cells down to sub-nanometer size of the switching layer as realized in the experiment are systematically studied, which indicates performance improvement and increased relative variability as the switching layer scales down. Finally, the results establish the ultimate limits of the size and energy scaling for CBRAM cells and illustrate the unique application of 2-D materials in ultralow power memory devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS1970

Improved solid state electron-charge-storage device

Storage device is applicable in memory systems and in high-resolution arrays for light-responsive image sensing. The device offers high yield in multiple arrays and allows charge release with light striking only the edge of a metal electrode.

Kuper, A. B.↗
NASA NTRS1991

Shape-memory alloy micro-actuator

A method of producing an integral piece of thermo-sensitive material, which is responsive to a shift in temperature from below to above a phase transformation temperature range to alter the material's condition to a shape-memory condition and move from one position to another. The method is characterized by depositing a thin film of shape-memory material, such as Nickel titanium (Ni-Ti) onto a substrate by vacuum deposition process such that the alloy exhibits an amorphous non-crystalline structure. The coated substrate is then annealed in a vacuum or in the presence of an inert atmosphere at a selected temperature, time and cool down rate to produce an ordered, partially disordered or fully disordered BCC structure such that the alloy undergoes thermoelastic, martinsetic phase transformation in response to alteration in temperature to pass from a martinsetic phase when at a temperature below a phase transformation range and capable of a high level of recoverable strain to a parent austenitic phase in a memory shape when at a temperature above the phase transformation range. Also disclosed are actuator devices employing shape-memory material actuators that deform from a set shape toward an original shape when subjected to a critical temperature level after having been initially deformed from the original shape into the set shape while at a lower temperature. The actuators are mechanically coupled to one or more movable elements such that the temperature-induce deformation of the actuators exerts a force or generates a motion of the mechanical element(s).

Busch, John D.↗