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At least 883 records · Page 49

Large-scale real-time signal processing in physics experiments: the ALICE TPC FPGA pipeline

For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.

Digital signal processing (DSP)↗

Experimental results from the characterization of a 32-channels mixed-signal processor for the GAPS experiment

This work describes the experimental results obtained from the characterization of a 32-channels readout ASIC that is the core of a module composed by 4 Lithium-drifted Silicon, Si(Li), detectors. The module is the building block of a tracker in an upcoming balloon experiment. The activity is carried out within the General AntiParticle Spectrometer (GAPS) international collaboration, whose objective is the indirect detection of dark matter through the detection of antiparticles present in cosmic rays at low energies. The balloon flight is foreseen in 2024 from the McMurdo station in Antarctica. The ASIC is designed in a 180 nm CMOS technology and has 32 low-noise analog readout channels featuring a dynamic compression of the signal, an 11-bit SAR ADC, and a digital back-end section responsible for channel setting and for sending digital information to the data acquisition system of the tracker. This work has a twofold goal: it intends on the one hand to verify the performance of the circuit, on the other to select at least 300 good samples to be used for the assembly of the GAPS Si(Li) tracker.

Riceputi, Elisa↗

Electronic system for optical shutter control

The paper describes a precise and versatile electronic system for shutter control in light beam experiments. Digital and analog circuitry is used to provide automatic timing, exposure control, manual operation, and remote programmability. A block diagram of the system is presented and the individual circuits - the timer control circuit, the clock control circuit, the comparator circuit, the exposure (integrator) circuit, and the shutter drive circuit are discussed in detail and diagrams are provided.

Viljoen, H. C.↗

Conceptual design of a data reduction system

A telemetry data processing system was defined of the Data Reduction. Data reduction activities in support of the developmental flights of the Space Shuttle were used as references against which requirements are assessed in general terms. A conceptual system design believed to offer significant throughput for the anticipated types of data reduction activities is presented. The design identifies the use of a large, intermediate data store as a key element in a complex of high speed, single purpose processors, each of which performs predesignated, repetitive operations on either raw or partially processed data. The recommended approach to implement the design concept is to adopt an established interface standard and rely heavily on mature or promising technologies which are considered main stream of the integrated circuit industry. The design system concept, is believed to be implementable without reliance on exotic devices and/or operational procedures. Numerical methods were employed to examine the feasibility of digital discrimination of FDM composite signals, and of eliminating line frequency noises in data measurements.

Source record↗

Test and evaluation of the generalized gate logic system simulator

The results of the initial testing of the Generalized Gate Level Logic Simulator (GGLOSS) are discussed. The simulator is a special purpose fault simulator designed to assist in the analysis of the effects of random hardware failures on fault tolerant digital computer systems. The testing of the simulator covers two main areas. First, the simulation results are compared with data obtained by monitoring the behavior of hardware. The circuit used for these comparisons is an incomplete microprocessor design based upon the MIL-STD-1750A Instruction Set Architecture. In the second area of testing, current simulation results are compared with experimental data obtained using precursors of the current tool. In each case, a portion of the earlier experiment is confirmed. The new results are then viewed from a different perspective in order to evaluate the usefulness of this simulation strategy.

Miner, Paul S.↗

Initial evaluation of commercially available InGaAsP DFB laser diodes for use in high-speed digital fiber optic transceivers

NASA has been pursuing the development of high-speed fiber-optic transceivers for use in a number of space data system applications. Current efforts are directed toward a high-performance all-integrated-circuit transceiver operating up to the 3-5 Gb/s range. Details of the evaluation and selection of candidate high-speed optical sources to be used in the space-qualified high-performance transceiver are presented. Data on the performance of commercially available DFB (distributed feedback) lasers are presented, and their performance relative to each other and to their structural design with regard to their use in high-performance fiber-optic transceivers is discussed. The DFB lasers were obtained from seven commercial manufacturers. The data taken on each laser included threshold current, differential quantum efficiency, CW side mode suppression radio, wavelength temperature coefficient, threshold temperature coefficient, natural linewidth, and far field pattern. It was found that laser diodes with buried heterostructures and first-order gratings had, in general, the best CW operating characteristics. The modulated characteristics of the DFB laser diodes are emphasized. Modulated linewidth, modulated side mode suppression ratio, and frequency response are discussed.

Cook, Anthony L.↗

Photodetector Array For Neural Network

Integrated circuit performs 1,024 threshold operations in parallel. Designed for use in postprocessing output of optical correlator in optoelectronic neural network. Overall function of device to put out digital signals indicative of location(s) of bright spot(s) on detector plane. Response time less than commercial charge-coupled-device (CCD) imaging detector operating at standard television frame rate.

Langenbacher, Harry↗

Practical design of magnetic heading sensors

Although fluxgate magnetometers have been in use for many years, and a number of theoretical studies of these sensors are available, very little information has been published on the engineering choices relating to the detailed design of magnetometers intended for navigational applications in aircraft and other vehicles. This paper addresses some of the problems encountered in the design of the sensing head, the choice of operating mode, and the design of the supporting electronics for a simple low-cost magnetometer system which will produce a digital readout of the magnetic heading of the vehicle in which it is mounted. A major goal of this study has been to develop a design which minimizes circuit complexity, is easy to fabricate and calibrate, and utilizes a minimum of specialized components. Such a magnetometer system is intended either as a stand-alone indicating instrument or as a source of magnetic heading information for a more sophisticated navigational system.

Garner, H. D.↗

Fundamentals of Digital Engineering: Designing for Reliability

The concept of designing for reliability will be introduced along with a brief overview of reliability, redundancy and traditional methods of fault tolerance is presented, as applied to current logic devices. The fundamentals of advanced circuit design and analysis techniques will be the primary focus. The introduction will cover the definitions of key device parameters and how analysis is used to prove circuit correctness. Basic design techniques such as synchronous vs asynchronous design, metastable state resolution time/arbiter design, and finite state machine structure/implementation will be reviewed. Advanced topics will be explored such as skew-tolerant circuit design, the use of triple-modular redundancy and circuit hazards, device transients and preventative circuit design, lock-up states in finite state machines generated by logic synthesizers, device transient characteristics, radiation mitigation techniques. worst-case analysis, the use of timing analyzer and simulators, and others. Case studies and lessons learned from spaceflight designs will be given as examples

Katz, R.↗

NASA Tech Briefs, July 2004

Topics: Optoelectronic Sensor System for Guidance in Docking; Hybrid Piezoelectric/Fiber-Optic Sensor Sheets; Multisensor Arrays for Greater Reliability and Accuracy; Integrated-Optic Oxygen Sensors; Ka-Band Autonomous Formation Flying Sensor; CMOS VLSI Active-Pixel Sensor for Tracking; Lightweight, Self-Deploying Foam Antenna Structures; Electrically Small Microstrip Quarter-Wave Monopole Antennas; A 2-to-28-MHz Phase-Locked Loop; Portable Electromyograph; Open-Source Software for Modeling of Nanoelectronic Devices; Software for Generating Strip Maps from SAR Data; Calibration Software for use with Jurassicprok; Software for Probabilistic Risk Reduction; Software Processes SAR Motion-Measurement Data; Improved Method of Purifying Carbon Nanotubes; Patterned Growth of Carbon Nanotubes or Nanofibers; Lightweight, Rack-Mountable Composite Cold Plate/Shelves; SiC-Based Miniature High-Temperature Cantilever Anemometer; Inlet Housing for a Partial-Admission Turbine; Lightweight Thermoformed Structural Components and Optics; Growing High-Quality InAs Quantum Dots for Infrared Lasers; Selected Papers on Protoplanetary Disks; Module for Oxygenating Water without Generating Bubbles; Coastal Research Imaging Spectrometer; Rapid Switching and Modulation by use of Coupled VCSELs; Laser-Induced-Fluorescence Photogrammetry and Videogrammetry; Laboratory Apparatus Generates Dual-Species Cold Atomic Beam; Laser Ablation of Materials for Propulsion of Spacecraft; Small Active Radiation Monitor; Hybrid Image-Plane/Stereo Manipulation; Partitioning a Gridded Rectangle into Smaller Rectangles; Digital Radar-Signal Processors Implemented in FPGAs; Part 1 of a Computational Study of a Drop-Laden Mixing Layer; and Some Improvements in Signal-Conditioning Circuits.

Source record↗

Re-Configurable Electronics Characterization under Extreme Thermal Environment

The need for reconfigurable electronics is driven by requirements to survive longer missions and harsher environments. It is possible to compensate for degradations in Extreme Environments (EE). EE has effect on electronics: circuits are designed to exploit device characteristics and when a certain temperature or radiation range is exceeded the circuit function gradually degrades. It is possible to employ Hardening by reconfiguration (HBR) to mitigate drifts, degradation, or damage on electronic devices in EE by using reconfigurable devices and an adaptive self-reconfiguration of circuit topology. In this manner degraded components can be salvaged, and completely damaged components can be bypassed. The challenge of conventional design is replaced with that of designing a recover process that automatically performs the (re) design in place of the designer. The objective of testing a Digital Signal Processor (DSP) under the extreme temperatures was to determine the lowest temperature at which the DAP can operate. The objective of testing a Xilinx VirtexII Pro FPGA board was to initially find our whether the evaluation board and the FPGA would survive and continue at temperature ranges from -180 C, and 120 C. The Virtex II functioned correctly at the temperatures tested. The next test was done on the GM-C filter building block using the same temperature range as the Virtex II. The current lower and upper limits were shown to be reduced as the temperature gets lower. The device function can be recovered by increasing the Vb from .08V to .85V. The negative and positive saturation voltages increases as the temperature gets higher. The function of the device can be recovered by decreasing the Vb from .8V to around .75V. The next test was performed to test the recovery of the GmC low pass filter through Vb in a filter circuit. The test indicate that bias voltage control adjustment is an efficient mechanism for circuit recovery at extreme temperatures.

reliability↗

Long period pseudo random number sequence generator

A circuit for generating a sequence of pseudo random numbers, (A sub K). There is an exponentiator in GF(2 sup m) for the normal basis representation of elements in a finite field GF(2 sup m) each represented by m binary digits and having two inputs and an output from which the sequence (A sub K). Of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs (E sub K) of maximal length shift register of n stages. There is a switch having a pair of inputs and an output. The switch outputs is connected to the other of the two inputs of the exponentiator. One of the switch inputs is connected for initially receiving a primitive element (A sub O) in GF(2 sup m). Finally, there is a delay circuit having an input and an output. The delay circuit output is connected to the other of the switch inputs and the delay circuit input is connected to the output of the exponentiator. Whereby after the exponentiator initially receives the primitive element (A sub O) in GF(2 sup m) through the switch, the switch can be switched to cause the exponentiator to receive as its input a delayed output A(K-1) from the exponentiator thereby generating (A sub K) continuously at the output of the exponentiator. The exponentiator in GF(2 sup m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U(sub i) = 92(sup i) (for n(sub i) = 1 or 1 (for n(subi) = 0).

Wang, Charles C.↗

Digital zero noise extrapolation for quantum error mitigation

Zero-noise extrapolation (ZNE) is an increasingly popular technique for mitigating errors in noisy quantum computations without using additional quantum resources. We review the fundamentals of ZNE and propose several improvements to noise scaling and extrapolation, the two key components in the technique. We introduce unitary folding and parameterized noise scaling. Furthermore, these are digital noise scaling frameworks, i.e. one can apply them using only gate-level access common to most quantum instruction sets. We also study different extrapolation methods, including a new adaptive protocol that uses a statistical inference framework. Benchmarks of our techniques show error reductions of 18X to 24X over non-mitigated circuits and demonstrate ZNE effectiveness at larger qubit numbers than have been tested previously. In addition to presenting new results, this work is a self-contained introduction to the practical use of ZNE by quantum programmers.

quantum computing↗

Time-division multiplexer uses digital gates

Device eliminates errors caused by analog gates in multiplexing a large number of channels at high frequency. System was designed for use in aerospace work to multiplex signals for monitoring such variables as fuel consumption, pressure, temperature, strain, and stress. Circuit may be useful in monitoring variables in process control and medicine as well.

Myers, C. E.↗

Optimization-Based Data-Driven Approach for Detecting Fault Location in Power Systems

In grids with large penetration of converterinterfaced resources (CIRs), measurements of voltage, current, and line parameters can fluctuate significantly during fault conditions. These fluctuations, combined with complex network topologies and extensive system branching, make accurate fault location challenging. Faults, such as short circuits, can cause prolonged outages with serious socio-economic impacts, highlighting the need for rapid fault identification to minimize downtime. However, current fault detection methods—such as relays and digital fault recorders—often relay information too slowly, impeding swift corrective action. Given the limited availability of high-resolution phasor measurement units, this paper introduces an optimization-based observer to estimate fault locations, grid line parameters, and voltages using local CIR measurements. To preserve the confidentiality of CIRs and enhance estimation accuracy, this study uses a black-box model of CIRs. This bottom-up, event-driven approach can enhances protection and control systems through optimized and real-time fault detection. Simulation results show that the optimization-based data-driven observer can accurately detect fault locations and estimate grid states and parameters, providing valuable insights for utilities and operators in grid applications.

Subedi, Sunil [ORNL] (ORCID:000000034069090X)↗

Data Transport Subsystem - The SFOC glue

The design and operation of the Data Transport Subsystem (DTS) for the JPL Space Flight Operation Center (SFOC) are described. The SFOC is the ground data system under development to serve interplanetary space probes; in addition to the DTS, it comprises a ground interface facility, a telemetry-input subsystem, data monitor and display facilities, and a digital TV system. DTS links the other subsystems via an ISO OSI presentation layer and an LAN. Here, particular attention is given to the DTS services and service modes (virtual circuit, datagram, and broadcast), the DTS software architecture, the logical-name server, the role of the integrated AI library, and SFOC as a distributed system.

Parr, Stephen J.↗

MQW Optical Feedback Modulators And Phase Shifters

Laser diodes equipped with proposed multiple-quantum-well (MQW) optical feedback modulators prove useful in variety of analog and digital optical-communication applications, including fiber-optic signal-distribution networks and high-speed, low-crosstalk interconnections among super computers or very-high-speed integrated circuits. Development exploits accompanying electro-optical aspect of QCSE - variation in index of refraction with applied electric field. Also exploits sensitivity of laser diodes to optical feedback. Approach is reverse of prior approach.

Jackson, Deborah J.↗

Solid-state image sensor with focal-plane digital photon-counting pixel array

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

Fossum, Eric R.↗