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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 865 records · Page 48
All sourcesNASA NTRSDOE OSTI
NASA NTRS1978

Determination of bulk diffusion lengths for angle-lapped semiconductor material via the scanning electron microscope: A theoretical analysis

A standard procedure for the determination of the minority carrier diffusion length by means of a scanning electron microscope (SEM) consists in scanning across an angle-lapped surface of a P-N junction and measuring the resultant short circuit current I sub sc as a function of beam position. A detailed analysis of the I sub sc originating from this configuration is presented. It is found that, for a point source excitation, the I sub sc depends very simply on x, the variable distance between the surface and the junction edge. The expression for the I sub sc of a planar junction device is well known. If d, the constant distance between the plane of the surface of the semiconductor and the junction edge in the expression for the I of a planar junction is merely replaced by x, the variable distance of the corresponding angle-lapped junction, an expression results which is correct to within a small fraction of a percent as long as the angle between the surfaces, 2 theta sub 1, is smaller than 10 deg.

Vonroos, O.↗
NASA NTRS1999

Photonic Switching Devices Using Light Bullets

A unique ultra-fast, all-optical switching device or switch is made with readily available, relatively inexpensive, highly nonlinear optical materials. which includes highly nonlinear optical glasses, semiconductor crystals and/or multiple quantum well semiconductor materials. At the specified wavelengths. these optical materials have a sufficiently negative group velocity dispersion and high nonlinear index of refraction to support stable light bullets. The light bullets counter-propagate through, and interact within the waveguide to selectively change each others' directions of propagation into predetermined channels. In one embodiment, the switch utilizes a rectangularly planar slab waveguide. and further includes two central channels and a plurality of lateral channels for guiding the light bullets into and out of the waveguide. An advantage of the present all-optical switching device lies in its practical use of light bullets, thus preventing the degeneration of the pulses due to dispersion and diffraction at the front and back of the pulses. Another advantage of the switching device is the relative insensitivity of the collision process to the time difference in which the counter-propagating pulses enter the waveguide. since. contrary to conventional co-propagating spatial solitons, the relative phase of the colliding pulses does not affect the interaction of these pulses. Yet another feature of the present all-optical switching device is the selection of the light pulse parameters which enables the generation of light bullets in nonlinear optical materials. including highly nonlinear optical glasses and semiconductor materials such as semiconductor crystals and/or multiple quantum well semiconductor materials.

Goorjian, Peter M.↗
NASA NTRS1982

Polycrystalline silicon availability for photovoltaic and semiconductor industries

Markets, applications, and production techniques for Siemens process-produced polycrystalline silicon are surveyed. It is noted that as of 1982 a total of six Si materials suppliers were servicing a worldwide total of over 1000 manufacturers of Si-based devices. Besides solar cells, the Si wafers are employed for thyristors, rectifiers, bipolar power transistors, and discrete components for control systems. An estimated 3890 metric tons of semiconductor-grade polycrystalline Si will be used in 1982, and 6200 metric tons by 1985. Although the amount is expected to nearly triple between 1982-89, research is being carried out on the formation of thin films and ribbons for solar cells, thereby eliminating the waste produced in slicing Czolchralski-grown crystals. The free-world Si production in 1982 is estimated to be 3050 metric tons. Various new technologies for the formation of polycrystalline Si at lower costs and with less waste are considered. New entries into the industrial Si formation field are projected to produce a 2000 metric ton excess by 1988.

Ferber, R. R.↗
NASA NTRS1967

Thin film process forms effective electrical contacts on semiconductor crystals

Process makes microscopic, low-resistance electrical contacts on hexagonal n-type silicon carbide crystals used for microelectronic devices. A vacuum deposition of aluminum is etched to expose the bare silicon carbide where the electrical contacts are made. Sputtering alternating layers of tantalum and gold forms the alloy film.

Formigoni, N. P.↗
NASA NTRS1972

Development of high temperature, high radiation resistant silicon semiconductors

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Whorl, C. A.↗
NASA NTRS1998

Characterization of PVT Grown ZnSe by Low Temperature Photoluminescence

ZnSe, a II-VI semiconductor with a large direct band gap of 2.7 eV at room temperature and 2.82 eV at 10 K, is considered a promising material for optoelectric applications in the blue-green region of the spectrum. Photoemitting devices and diode laser action has been demonstrated as a result of decades of research. A key issue in the development of II-VI semiconductors is the control of the concentration of the various impurities. The II-VI semiconductors seem to defy the effort of high level doping due to the well known self compensation of the donors and the acceptors. A good understanding of roles of the impurities and the behavior of the various intrinsic defects such as vacancies, interstitials and their complexes with impurities is necessary in the development and application of these materials. Persistent impurities such as Li and Cu have long played a central role in the photoelectronic properties of many II-VI compounds, particularly ZnSe. The shallow centers which may promote useful electrical conductivity are of particular interest. They contribute the richly structured near gap edge luminescence, containing weak to moderate phonon coupling and therefore very accessible information about the energy states of the different centers. Significance of those residual impurities which may contribute such centers in II-VI semiconductors must be fully appreciated before improved control of their electrical properties may be possible. Low temperature photoluminescence spectroscopy is an important source of information and a useful tool of characterization of II-VI semiconductors such as ZnSe. The low temperature photoluminescence spectrum of a ZnSe single crystal typically consists of a broad band emission peaking at 2.34 eV, known as the Cu-green band, and some very sharp lines near the band gap. These bands and lines are used to identify the impurity ingredients and the defects. The assessment of the quality of the crystal based on the photoluminescence analysis is then possible. In this report we present the characterization of a ZnSe single crystal as grown by the physical vapor transport method, with special intention paid to the possible effects of the gravitational field to the growth of the crystal.

Wang, Ling Jun↗
NASA NTRS1985

Damping Relaxation Oscillations in Laser Diodes

Proposed semiconductor laser modulated at frequencies up to near its resonant frequency more efficiently than older devices. New laser uses two different effective carrier lifetimes: one for dc and lowfrequency operation and another for operation near resonant frequency. Laser part of bipolar transistor with capacitor that serves as ac short circuit.

Katz, J.↗
NASA NTRS1989

Molecular-Beam Epitaxy Of CrSi2 on Si(111)

Crystalline layers grown in commercial apparatus. Experiments show CrSi2 grown on (111) face of single-crystal Si substrate by molecular-beam epitaxy. Epitaxial CrSi2 produced thus far not in desired single-crystal form. Because CrSi2 semiconductor with band gap of 0.3 eV, experimental process potential for monolitic integration of microelectronic devices based on CrSi2 (e.g., infrared detectors) with signal-processing circuitry based on Si.

Fathauer, Robert W.↗
NASA NTRS1989

Chemical profiling of silicon nitride structures

X ray photoelectron spectroscopy (XPS), spectroscopic ellipsometry (SE), and scanning electron microscopy (SEM) were used to study structural and chemical inhomogeneities in several electronic materials and device structures of relevance to radiation hard electronics. The systems studied include metal nitride oxide semiconductor (MNOS) structures, silicon oxynitride (SiO(x)N(y)) formed by the thermal nitridation of SiO2, and semiconductor on insulator (SOI) structures. Studies of MNOS structures suggest that the effect of H2 annealing is to make the Si3N4/SiO2 interface less abrupt by causing interdiffusion of silanol and silamine groups with subsequent oxynitride formation. Another effect of the annealing appears to be to relieve the strain at the SiO2/Si interface.

Vasquez, R. P.↗
NASA NTRS1990

Electron beam induced damage in PECVD Si3N4 and SiO2 films on InP

Phosphorus rich plasma enhanced chemical vapor deposition (PECVD) of silicon nitride and silicon dioxide films on n-type indium phosphide (InP) substrates were exposed to electron beam irradiation in the 5 to 40 keV range for the purpose of characterizing the damage induced in the dielectic. The electron beam exposure was on the range of 10(exp -7) to 10(exp -3) C/sq cm. The damage to the devices was characterized by capacitance-voltage (C-V) measurements of the metal insulator semiconductor (MIS) capacitors. These results were compared to results obtained for radiation damage of thermal silicon dioxide on silicon (Si) MOS capacitors with similar exposures. The radiation induced damage in the PECVD silicon nitride films on InP was successfully annealed out in an hydrogen/nitrogen (H2/N2) ambient at 400 C for 15 min. The PECVD silicon dioxide films on InP had the least radiation damage, while the thermal silicon dioxide films on Si had the most radiation damage.

Pantic, Dragan M.↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS1995

Reshaping Light-Emitting Diodes To Increase External Efficiency

Light-emitting diodes (LEDs) reshaped, according to proposal, increasing amount of light emitted by decreasing fraction of light trapped via total internal reflection. Results in greater luminous output power for same electrical input power; greater external efficiency. Furthermore, light emitted by reshaped LEDs more nearly collimated (less diffuse). Concept potentially advantageous for conventional red-emitting LEDs. More advantageous for new "blue" LEDs, because luminous outputs and efficiencies of these devices very low. Another advantage, proposed conical shapes achieved relatively easily by chemical etching of semiconductor surfaces.

Rogowski, Robert↗
NASA NTRS2012

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

Duong, Tuan A.↗
NASA NTRS1995

Preparation of Thermoelectric Materials from Melts

The most common methods to prepare semiconductors are based on use of melts or vapor phase. A tendency to use thin film structures in modern semiconducting devices brought a variety of technologies based on vapor phase deposition. The preparation of chemical compounds and solid solutions from a melt begins with melting the elemental constituents together. Melt technology and techniques are discussed.

thermoelectric↗
NASA NTRS2019

Performance Evaluation of High-Speed, Low-Side Gate Driver, FAN3122, over Extended Temperature Range

Emerging power metal-oxide semiconductor field-effect transistor (MOSFETs) based on silicon carbide and gallium nitride technology are finding widespread use in many electronic applications such as motor control and DC/DC converters due to their higher voltage, higher temperature tolerance, and higher frequency switching capabilities. To utilize these power devices and to meet circuit/system compactness, modularity, and operational functionality, gate drivers that provide unique attributes, such as fast switching and high-current handling capability, are needed. In addition, power systems geared for use in space mission applications require on-board devices to withstand exposure to extreme temperatures and wide thermal swings. Very little data, however, exist on the performance of such devices and circuits under extreme temperatures. In this work, the performance of a high-speed gate driver with potential use in controlling power-level transistors was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.

Wide Bandgap Semiconductors↗
NASA NTRS2019

Standardizing Microprocessor and GPU Radiation Test Approaches

Microprocessor, Graphics Processing Units (GPUs) and DDRx memory devices have emerged as promising next-generation technologies that enables both high performance processing and acceleration of complex algorithms for the latest challenges in human spaceflight, autonomous vehicles and artificial intelligence (AI). The feature sets of these devices offer exponential increases to throughput, calculation capability and system autonomy when compared to legacy flight systems. NASA's Electronic Part and Packaging (NEPP) Program has conducted an investigation into the radiation susceptibility of leading edge devices and process technologies by establishing standardized test approaches. Unlike most discrete devices, these require state of the art test systems to induce specific hardware activity similar to application software, thus allowing the characterization of failure modes within the system. To best characterize the tested part, NEPP eliminates variables that may impact device performance under radiation. Simplification of remaining system-level variables leads to an improved understanding of complex computational devices and their intended applications. The failure modes and error signatures that are recorded during testing are used to determine radiation sensitivity of the semiconductor process and the microcode architecture of the design. This presentation will discuss the test methodology that NASA Electronic Parts and Packaging (NEPP) is working to establish for its microprocessor, GPU and DDRx memory test programs to provide guidance on these devices and their underlying technology, in regards to their potential usage in future space flight systems.

GPU↗