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At least 865 records · Page 48
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Coupling Between Microstrip Lines and Finite Ground Coplanar Lines Embedded in Polyimide Layers for 3D-MMICs on Silicon

Three-dimensional circuits built upon multiple layers of polyimide are required for constructing Si/SiGe monolithic microwave/mm-wave integrated circuits on CMOS (low resistivity) Si wafers. It is expected that these circuits will replace the ones fabricated on GaAs and reduce the overall system cost. However, the closely spaced transmission lines that are required for a high-density circuit environment are susceptible to high levels of cross-coupling, which degrades the overall circuit performance. In this paper, theoretical and experimental results on coupling and ways to reduce it are presented for two types of transmission lines: a) the microstrip line and b) the Finite Ground Coplanar (FGC) line. For microstrip lines it is shown that a fence of metalized via-holes can significantly reduce coupling, especially in the case when both lines are on the same polyimide layer or when the shielding structure extends through several polyimide layers. For closely spaced microstrip lines, coupling is lower for a metal filled trench shield than a via-hole fence. Coupling amongst microstrip lines is dependent on the ratio of line separation to polyimide thickness and is primarily due to magnetic fields. For FGC lines it is shown that they have in general low coupling that can be reduced significantly when there is even a small gap between the ground planes of each line. FGC lines have approximately 8 dB lower coupling than coupled coplanar waveguides (CPW). In addition, forward and backward characteristics of the FGC lines do not resemble those of other transmission lines such as microstrip. Therefore, the coupling mechanism of the FGC lines is different compared to thin film microstrip lines.

Ponchak, G. E.↗
NASA NTRS1994

Optoelectronic Receiver For Communication And Control

Many operational and diagnostic features integrated into circuit chip. GaAs-based integrated circuit designed to serve as optoelectronic interface in phased-array antenna. Intended function to receive digital control signals transmitted on optical fiber and to convert signals to electronic control signals, which then applied to monolithic microwave integrated circuit (MMIC). Also used in reception of high-rate optical digital communications within computers, between computers, and in signal-distribution systems in aircraft, automobiles, and ships. Interface circuit represents significant improvement over preexisting interface circuits in that its clock-signal-recovery subcircuit requires little or no preamble for immediate synchronization.

Kunath, Richard↗
NASA NTRS1986

Simulating Single-Event Upsets in Bipolar RAM's

Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.

Zoutendyk, J. A.↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
DOE OSTI2024

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗
NASA NTRS2008

Integrator Circuitry for Single Channel Radiation Detector

Input circuitry is provided for a high voltage operated radiation detector to receive pulses from the detector having a rise time in the range of from about one nanosecond to about ten nanoseconds. An integrator circuit, which utilizes current feedback, receives the incoming charge from the radiation detector and creates voltage by integrating across a small capacitor. The integrator utilizes an amplifier which closely follows the voltage across the capacitor to produce an integrator output pulse with a peak value which may be used to determine the energy which produced the pulse. The pulse width of the output is stretched to approximately 50 to 300 nanoseconds for use by subsequent circuits which may then use amplifiers with lower slew rates.

Holland, Samuel D.↗
NASA NTRS2009

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy↗
DOE OSTI2020

Integrated dispersion compensated mode-locked quantum dot laser

Quantum dot lasers are excellent on-chip light sources, offering high defect tolerance, low threshold, low temperature variation, and high feedback insensitivity. Yet a monolithic integration technique combining epitaxial quantum dot lasers with passive waveguides has not been demonstrated and is needed for complex photonic integrated circuits. We present here, for the first time to our knowledge, a monolithc offset quantum dot integration platform that permits formation of a laser cavity utilizing both the robust quantum dot active region and the versatility of passive GaAs waveguide structures. This platform is substrate agnostic and therefore compatible with the quantum dot lasers directly grown on Si. As an illustration of the potential of this platform, we designed and fabricated a 20 GHz mode-locked laser with a dispersion-engineered on-chip waveguide mirror. Due to the dispersion compensation effect of the waveguide mirror, the pulse width of the mode-locked laser is reduced by a factor of 2.8.

Zhang, Zeyu (ORCID:0000000271576272)↗
NASA NTRS1985

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS2001

Coupling between Microstrip Lines Embedded in Polyimide Layers for 3D-MMICs on Si

Three-dimensional circuits built upon multiple layers of polyimide are required for constructing SilSiGe monolithic microwavdmillimeter-wave integrated circuits on CMOS (low resistivity) Si wafers. However, the closely spaced transmission lines are susceptible to high levels of coupling, which degrades circuit performance. In this paper, Finite Difference Time Domain (FDTD) analysis and measured characteristics of novel shielding structures that significantly reduce coupling between embedded microstrip lines are presented. A discussion of the electric and magnetic field distributions for the coupled microstrip lines is presented to provide a physical rationale for the presented results.

Ponchak, George E.↗
NASA NTRS2009

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Samoska, Lorene↗
NASA NTRS2011

Circuit for Communication Over Power Lines

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

Krasowski, Michael J.↗
DOE OSTI2021

Demonstration of a MOT in a sub-millimeter membrane hole

Abstract We demonstrate the generation of a cold-atom ensemble within a sub-millimeter diameter hole in a transparent membrane, a so-called “membrane MOT”. With a sub-Doppler cooling process, the atoms trapped by the membrane MOT are cooled down to 10 $$\upmu$$ μ K. The atom number inside the unbridged/bridged membrane hole is about $$10^4$$ 10 4 to $$10^5$$ 10 5 , and the $$1/e^2$$ 1 / e 2 -diameter of the MOT cloud is about 180 $$\upmu$$ μ m for a 400 $$\upmu$$ μ m-diameter membrane hole. Such a membrane device can, in principle, efficiently load cold atoms into the evanescent-field optical trap generated by the suspended membrane waveguide for strong atom-light interaction and provide the capability of sufficient heat dissipation at the waveguide. This represents a key step toward the photonic atom trap integrated platform (ATIP).

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS1979

Miniature Ku-Band down converter

Hybrid circuit serves as receiver front end for 13.75- to 14.0-GHz communications and radar systems. Complete microwave integrated circuit (MIC) assembly is packaged in small hermetically welded, nitrogen-filled aluminum case. Simplicity and size proves useful for lower-frequency wideband applications.

Norbury, D. A.↗
NASA NTRS1980

Inductorless tuned circuit for high frequencies

Inductorless tuned circuit functions as filter, amplifier, or oscillator at radio frequencies. Circuit is based on two directly-coupled transistors operated at their transition frequency and fabricated as integrated circuit on single silicon chip.

Kleinberg, L.↗