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At least 865 records · Page 48

Nutrient Limitation Predisposes A Cultivate of Burkholderia Contaminans From the ISS Water Processor Assembly to Biofilm Formation Under Simulated Microgravity.

The International Space Station (ISS) Water Processor Assembly (WPA) experiences intermittent dormancy between water recycling events thus promoting biofilm formation within the system. In this work we aimed to gain a deeper understanding of the impact of nutrient limitation on bacterial growth and biofilm formation under microgravity in support of biofilm mitigation efforts in exploration water recovery systems. A representative species of bacteria that is commonly cultured from the ISS WPA was cultured in an WPA influent water ersatz formulation tailored for microbiology studies. Burkholderia contaminans was cultured under a simulated microgravity (SµG) treatment in a vertically rotating high-aspect rotating vessel (HARV), with a rotating control (R) in the horizontal plane at the determined optimal rpm of 15 along with a stationary (S) control. At different time points, the bacterial culture and ersatz were harvested for bacterial counts, transcriptomic and nutrient content analyses. Under the test conditions, the culture under SµG treatment consumed the essential nutrients faster than the R and S control cultures in the early stage of growth, thus approaching a nutrient limited growth condition earlier than the controls. The rapid uptake and subsequent depletion of essential nutrients was further illustrated in the transcriptomic response of the SµG culture when compared to the transcriptomic response of the R and S control conditions. The observed starvation response may serve as one element to explain a moderate enhancement of biofilm formation in the SµG treatment. One implication of this investigation is that biofilm mitigation in the ISS environment could be supported by ensuring a steady flow of water as a vehicle for essential nutrients within the WPA to avoid complete consumption which occurs in times of no flow lending to undesired biofilm formation.

Angie Diaz↗

Development and Testing of a New Partial Gravity Urine Processor Design and Urine Pretreatment

The Planetary Urine Processor (PUP) is a urine distillation system for lunar or planetary applications, taking advantage of local gravity for phase separation as well as the movement and storage of waste feeds and distillate. The PUP utilizes a stationary evaporator with an integrated disposable bag to process urine and capture remaining precipitates. This system aims to increase water reclamation percentage to greater than 96%, reduce resource requirements, and enhance reliability and maintainability due to lower system complexity over the existing water recovery system on the International Space Station (ISS). This paper focuses on the hardware development, testing efforts, and the associated urine pretreatment development work.

Water Recovery↗

Development and Testing of a New Partial Gravity Urine Processor Design and Urine Pretreatment

The Planetary Urine Processor (PUP) is a urine distillation system for lunar or planetary applications, taking advantage of local gravity for phase separation as well as the movement and storage of waste feeds and distillate. The PUP utilizes a stationary evaporator with an integrated disposable bag to process urine and capture remaining precipitates. This system aims to increase water reclamation percentage to greater than 96%, reduce resource requirements, and enhance reliability and maintainability due to lower system complexity over the existing water recovery system on the International Space Station (ISS). This paper focuses on the hardware development, testing efforts, and the associated urine pretreatment development work.

Water Recovery↗

Sample Processor for Life on Icy Worlds (SPLIce): Monolithic Manifold-Based System to Recover, Prepare, and Deliver Samples and Standards to Instrumentation Suites for Ocean World Life-Search Missions

A claim of life detection on one of the solar system’s icy ocean worlds would necessitate extraordinarily convincing evidence. Limited energy availability in the oceans of such bodies as Europa and Enceladus argues for microbes as most probable among possible life forms, but evidence of their existence in the surface layers of an icy moon or in a frozen plume ejected into space could take various forms, pointing to instrumentation suites as a preferred means to detect diverse molecular and morphological life indicators. Multiple disparate categories of positive detections could provide truly convincing evidence from samples that may be only a few micro-liters. SPLIce’s Foundation. Teams led by NASA’s Ames Research Center have developed and operated numerous small, live-biology and astrobiology science payloads in space over two decades. Since 2016, we have adapted and augmented their biological sample-handling systems to create compact, robust search-for-life fluidic processors designed to function after a decade or more in transit, in environments with very little gravity and lots of radiation: up to 100’s of kilorads.

Instrumentation suite↗

GVT Algorithms and Discrete Event Dynamics on 128K+ Processor Cores

Parallel discrete event simulation (PDES) represents a class of codes that are challenging to scale to large number of processors due to tight global timestamp-ordering and fine-grained event execution. One of the critical factors in scaling PDES is the efficiency of the underlying global virtual time (GVT) algorithm needed for correctness of parallel execution and speed of progress. Although many GVT algorithms have been proposed previously, few have been proposed for scalable asynchronous execution and none customized to exploit one-sided communication. Moreover, the detailed performance effects of actual GVT algorithm implementations on large platforms are unknown. Here, three major GVT algorithms intended for scalable execution on high-performance systems are studied: (1) a synchronous GVT algorithm that affords ease of implementation, (2) an asynchronous GVT algorithm that is more complex to implement but can relieve blocking latencies, and (3) a variant of the asynchronous GVT algorithm, proposed and studied for the first time here, to exploit one-sided communication in extant supercomputing platforms. Performance results are presented of implementations of these algorithms on over 64,000 cores of a Cray XT5 system, exercised on a range of parameters: optimistic and conservative synchronization, fine- to medium-grained event computation, synthetic and non-synthetic applications, and different lookahead values. Performance of tens of billions of events executed per second are registered, exceeding the speeds of any known PDES engine, and showing asynchronous GVT algorithms to outperform state-of-the-art synchronous GVT algorithms. Detailed PDES-specific runtime metrics are presented to further the understanding of tightly-coupled discrete event execution dynamics on massively parallel platforms.

99 GENERAL AND MISCELLANEOUS↗

System, methods and apparatus for program optimization for multi-threaded processor architectures

Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that allow for parallel execution of tasks. The first custom computing apparatus optimizes the code for parallelism, locality of operations and contiguity of memory accesses on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

42 ENGINEERING↗

QCD For Intel(R) Xeon Phi(tm) and Xeon(tm) processors

This library provides a library containing highly optimized Wilson-Dslash, Wilson Clover operator and Krylov subspace solvers for Lattice QCD simulations. The library is targeted at Intel(R) Xeon Phi(tm), and Intel(R) Xeon(tm) processors.

Joo, Balint↗

Processor Emulator with Benchmark Applications

A processor emulator and a suite of benchmark applications have been developed to assist in characterizing the performance of data-centric workloads on current and future computer architectures. Some of the applications have been collected from other open source projects. For more details on the emulator and an example of its usage, see reference [1].

Lloyd, G. Scott↗

Roofline Analysis in the Intel® Advisor to Deliver Optimized Performance for applications on Intel® Xeon Phi™ Processor

In this session we show, in two case studies, how the roofline feature of Intel Advisor has been utilized to optimize the performance of kernels of the XGC1 and PICSAR codes in preparation for Intel Knights Landing architecture. The impact of the implemented optimizations and the benefits of using the automatic roofline feature of Intel Advisor to study performance of large applications will be presented. This demonstrates an effective optimization strategy that has enabled these science applications to achieve up to 4.6 times speed-up and prepare for future exascale architectures. # Goal/Relevance of Session The roofline model [1,2] is a powerful tool for analyzing the performance of applications with respect to the theoretical peak achievable on a given computer architecture. It allows one to graphically represent the performance of an application in terms of operational intensity, i.e. the ratio of flops performed and bytes moved from memory in order to guide optimization efforts. Given the scale and complexity of modern science applications, it can often be a tedious task for the user to perform the analysis on the level of functions or loops to identify where performance gains can be made. With new Intel tools, it is now possible to automate this task, as well as base the estimates of peak performance on measurements rather than vendor specifications. The goal of this session is to demonstrate how the roofline feature of Intel Advisor can be used to balance memory vs. computation related optimization efforts and effectively identify performance bottlenecks. A series of typical optimization techniques: cache blocking, structure refactoring, data alignment, and vectorization illustrated by the kernel cases will be addressed. # Description of the codes ## XGC1 The XGC1 code [3] is a magnetic fusion Particle-In-Cell code that uses an unstructured mesh for its Poisson solver that allows it to accurately resolve the edge plasma of a magnetic fusion device. After recent optimizations to its collision kernel [4], most of the computing time is spent in the electron push (pushe) kernel, where these optimization efforts have been focused. The kernel code scaled well with MPI+OpenMP but had almost no automatic compiler vectorization, in part due to indirect memory addresses and in part due to low trip counts of low-level loops that would be candidates for vectorization. Particle blocking and sorting have been implemented to increase trip counts of low-level loops and improve memory locality, and OpenMP directives have been added to vectorize compute-intensive loops that were identified by Advisor. The optimizations have improved the performance of the pushe kernel 2x on Haswell processors and 1.7x on KNL. The KNL node-for-node performance has been brought to within 30% of a NERSC Cori phase I Haswell node and we expect to bridge this gap by reducing the memory footprint of compute intensive routines to improve cache reuse. ## PICSAR is a Fortran/Python high-performance Particle-In-Cell library targeting at MIC architectures first designed to be coupled with the PIC code WARP for the simulation of laser-matter interaction and particle accelerators. PICSAR also contains a FORTRAN stand-alone kernel for performance studies and benchmarks. A MPI domain decomposition is used between NUMA domains and a tile decomposition (cache-blocking) handled by OpenMP has been added for shared-memory parallelism and better cache management. The so-called current deposition and field gathering steps that compose the PIC time loop constitute major hotspots that have been rewritten to enable more efficient vectorization. Particle communications between tiles and MPI domain has been merged and parallelized. All considered, these improvements provide speedups of 3.1 for order 1 and 4.6 for order 3 interpolation shape factors on KNL configured in SNC4 quadrant flat mode. Performance is similar between a node of cori phase 1 and KNL at order 1 and better on KNL by a factor 1.6 at order 3 with the considered test case (homogeneous thermal plasma).

97 MATHEMATICS AND COMPUTING↗

Processor-in-memory-and-storage architecture

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

97 MATHEMATICS AND COMPUTING↗

Spasers to speed up CMOS processors

A processor includes a transistor pair of a first transistor and a second transistor. The first transistor of the transistor pair is coupled to a Spaser and configured to output a drive current to the Spaser to pump the Spaser. Responsive to the drive current, the Spaser outputs surface plasmon polaritons (SPPs) which are fed to a plasmonic interconnect wire. The plasmonic interconnect wire propagates the SPPs. Further, the SPPs propagated on the plasmonic interconnect wire are detected by a phototransistor. Responsive to detecting the SPPs, the phototransistor generates an output current that is fed to a gate terminal of the second transistor to charge the second transistor.

42 ENGINEERING↗

Processor power monitoring and control with dynamic load balancing

Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.

97 MATHEMATICS AND COMPUTING↗

Arrangements for communicating data in a computing system using multiple processors

Data employed in computations amongst multiple processors in a computing system is processed so that less bits than a full representation of the data needs to be communicated yet all of the relevant information is communicated. More specifically, a sensitivity value is determined for various items of the data which reflect the number of bits in the data items that are not garbage bits, and only information in the data items that are indicated by the sensitivity value to not be garbage bits are necessarily effectively retained. At least the information that is not garbage bits and the corresponding associated sensitivity are packed together. The results of computations that are performed using the data items as at least one of the operands for the computation are associated with a sensitivity that is derived from the individual sensitivities of the operands used in the computation.

Gonzalez, Juan Guillermo↗

Compressing micro-operations in scheduler entries in a processor

An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

Boyer, Michael W.↗

Quantum frequency processor for provable cybersecurity

Methods of quantum key distribution include receiving a frequency bin photon at a location, selecting a frequency bin photon quantum key distribution measurement basis, with a quantum frequency processor, performing a measurement basis transformation on the received frequency bin photon so that the frequency bin photon is measurable in the selected frequency bin photon quantum key distribution measurement basis, and detecting the frequency bin photon in the selected quantum key distribution measurement basis and assigning a quantum key distribution key value based on the detection to a portion of a quantum key distribution key. Apparatus and methods for encoding, decoding, transmitting, and receiving frequency bin photons are disclosed.

Lukens, Joseph M.↗

Filtering micro-operations for a micro-operation cache in a processor

A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.

Scrbak, Marko↗

Quantum frequency processor for provable cybersecurity

Methods of quantum key distribution include receiving a frequency bin photon at a location, selecting a frequency bin photon quantum key distribution measurement basis, with a quantum frequency processor, performing a measurement basis transformation on the received frequency bin photon so that the frequency bin photon is measurable in the selected frequency bin photon quantum key distribution measurement basis, and detecting the frequency bin photon in the selected quantum key distribution measurement basis and assigning a quantum key distribution key value based on the detection to a portion of a quantum key distribution key. Apparatus and methods for encoding, decoding, transmitting, and receiving frequency bin photons are disclosed.

Lukens, Joseph M.↗