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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 865 records · Page 48

All sources NASA NTRS DOE OSTI

NASA NTRS1990

An efficient optical architecture for sparsely connected neural networks

An architecture for general-purpose optical neural network processor is presented in which the interconnections and weights are formed by directing coherent beams holographically, thereby making use of the space-bandwidth products of the recording medium for sparsely interconnected networks more efficiently that the commonly used vector-matrix multiplier, since all of the hologram area is in use. An investigation is made of the use of computer-generated holograms recorded on such updatable media as thermoplastic materials, in order to define the interconnections and weights of a neural network processor; attention is given to limits on interconnection densities, diffraction efficiencies, and weighing accuracies possible with such an updatable thin film holographic device.

Hine, Butler P., III↗

NASA NTRS1993

Climbing robot

A mobile robot for traversing any surface consisting of a number of interconnected segments, each interconnected segment having an upper 'U' frame member, a lower 'U' frame member, a compliant joint between the upper 'U' frame member and the lower 'U' frame member, a number of linear actuators between the two frame members acting to provide relative displacement between the frame members, a foot attached to the lower 'U' frame member for adherence of the segment to the surface, an inter-segment attachment attached to the upper 'U' frame member for interconnecting the segments, a power source connected to the linear actuator, and a computer/controller for independently controlling each linear actuator in each interconnected segment such that the mobile robot moves in a caterpillar like fashion.

Kerley, James J.↗

NASA NTRS2005

Fiber Optic Repair and Maintainability (FORM) Program Progresses

Advanced aircraft will employ fiber-optic interconnection components to transmit information from airframe and propulsion sensors to the flight control computers. Although these optical interconnects have been rigorously tested under laboratory conditions to determine their operating and environmental limits, there is concern as to their repairability and maintainability when placed in actual service. The Fiber Optic Repair and Maintainability (FORM) flight test program will provide data to enable designers to improve these fiber-optic interconnection systems for the next generation of aircraft. FORM is identifying critical problems in installing, maintaining, testing, and repairing fiber-optic interconnection systems in an operational avionics environment. This program is a cooperative Government/industry effort to evaluate optical component acceptability and installation techniques for aircraft.

Source record↗

NASA NTRS2011

NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions

A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with sub-microsecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems. NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary. Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.

He, Yutao↗

NASA NTRS2017

Thermal cycling testing to failure of a ceramic column grid array package for space applications

Ceramic column grid array (CCGA) packages have been used increasingly in logic and microprocessor functions, telecommunications, flight avionics boards, payload electronics boards, engineering navigational and science cameras, electronic assemblies, and other applications, because of their inherent advantages such as high electrical interconnect density, very good thermal and electrical performance, and compatibility with standard surface-mount technology (SMT) packaging assembly processes. Because these advanced electronic packages tend to have less solder-joint strain-relief than do leaded flat-pack electronic packages, the reliability of CCGA packages in challenging thermal environments is a very important consideration for their short- and long-term use in JPL-NASA space missions. In this study, we assembled daisy chains of polyimide printed wiring boards from CCGA-interconnect packages, inspected the boards nondestructively, and then subjected them to thermal cycling to assess their reliability in thermal environments from +125°C to -40°C±25°C. The test hardware consists of a CCGA 1752 package (CN version). The package was divided into four daisy-chained sections that were electrically monitored for their continuity during thermal cycling. The CCGA 1752 package is roughly 45 mm × 45 mm with a 42-mm × 42-mm array of 80%/20% Pb/Sn columns on a 1.00-mm pitch. The resistance of the daisy-chained CCGA interconnects was continuously monitored during thermal cycling in a gaseous nitrogen environment. Electrical continuity resistance measurements as a function of thermal cycling are reported here; tests to date have shown significant change to an open circuit in daisy-chain resistance as a function of thermal cycling. The change in interconnect resistance becomes increasingly noticeable with increasing number of thermal cycles. This paper describes the experimental thermal-cycling test results of CCGA 1752 package reliability testing under an extremely wide temperature range. The first failure was observed at 1479th thermal cycle. We report the thermal-cycle reliability test data for ~2500 thermal cycles.

Ramesham, Rajeshuni↗

DOE OSTI2015

Formed photovoltaic module busbars

A cell connection piece for a photovoltaic module is disclosed herein. The cell connection piece includes an interconnect bus, a plurality of bus tabs unitarily formed with the interconnect bus, and a terminal bus coupled with the interconnect bus. The plurality of bus tabs extend from the interconnect bus. The terminal bus includes a non-linear portion.

14 SOLAR ENERGY↗

DOE OSTI2015

Induction soldering of photovoltaic system components

A method comprises positioning a pair of photovoltaic wafers in a side-by-side arrangement. An interconnect is placed on the pair of wafers such that the interconnect overlaps both wafers of the pair, solder material being provided between the interconnect and the respective wafers. A solder head is then located adjacent the interconnect, and the coil is energized to effect inductive heating of the solder material. The solder head comprises an induction coil shaped to define an eye, and a magnetic field concentrator located at least partially in the eye of the coil. The magnetic field concentrator defines a passage extending axially through the eye of the coil, and may be of a material with a high magnetic permeability.

14 SOLAR ENERGY↗

DOE OSTI2018

Formed photovoltaic module busbars

A photovoltaic system including a cell connection piece coupled to a plurality of photovoltaic cells and a terminal of a junction box. The cell connection piece includes an interconnect bus, a plurality of bus tabs unitarily formed with the interconnect bus, and a terminal bus coupled with the interconnect bus. The plurality of bus tabs extend from the interconnect bus. The terminal bus includes a nonlinear portion.

14 SOLAR ENERGY↗

DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗

DOE OSTI2021

Additive Manufacturing of Frequency-Agile W-Band Packaging

Abstract —In this paper we demonstrate a fully additively manufactured packaged W-band amplifier with integrated bypass capacitors. This package was fabricated using a chip-first approach and aerosol jet printing. Package substrates (dielectrics), conductors and interconnects are printed around a bare die attached to a carrier. This package uses shaped ramp interconnects, allowing for frequency agnostic package performance of the interconnect with no impedance discontinuity, within the physical limits of the printer. High dielectric constant thin films of a polymer-matrix nanocomposite for bypass capacitors were printed using multi-material aerosol jet printing. The maximum measured packaged gain is 14.9 dB in the W-band, compared to the maximum bare die gain of 15.5 dB in the same frequency range. From 75 - 92 GHz, the average package loss is 1.1 dB including 3 mm transmission line, interconnects, and a GSG launch structure correlating to an average loss of 0.37 dB/mm.

Additive manufacturing, aerosol jet printing, hete↗

DOE OSTI2022

Coolant delivery via an independent cooling circuit

An embodiment of an independent cooling circuit for selectively delivering cooling fluid to a component of a gas turbine system includes: at least one coolant feed channel fluidly coupled to a supply of cooling fluid; and an interconnected circuit of cooling channels, including: an interconnected circuit of cooling channels embedded within an exterior wall of the component; an impingement plate; and a plurality of feed tubes connecting the impingement plate to the exterior wall of the component and fluidly coupling a supply of cooling fluid to the interconnected circuit of cooling channels; wherein the cooling fluid flows through the plurality of feed tubes into the interconnected circuit of cooling channels only in response to a formation of a breach in the exterior wall of the component that exposes at least one of the cooling channels.

42 ENGINEERING↗

DOE OSTI2023

Modular base for an antenna array

A base configured to be joined with other bases to form a substrate for an antenna array comprises a body, a plurality of male interconnecting features, and a plurality of female interconnecting features. The body includes a front surface and a rear surface and a plurality of edges positioned therebetween. The front surface or the rear surface is configured to retain an antenna. The male interconnecting features of a first base connect with the female interconnecting features of a second base when the first base is joined with the second base to form the substrate or a portion of the substrate.

Furman, Nicholas J.↗

DOE OSTI2025

OR-AGENT framework – Architecting electrified heavy-duty drayage applications

The widespread adoption of zero-emission vehicles in heavy-duty (HD) commercial freight transportation faces considerable technoeconomic challenges. For heavy-duty trucks, ensuring high uptime, cost parity with diesel, and safety standards is especially critical as these vehicles operate over long distances with heavy loads, where any downtime or off-nominal behaviors significantly impacts logistics, productivity, and the total cost of ownership. Unlike traditional diesel refueling, BEV charging infrastructure must be co-optimized with vehicle deployment, operational demands, and grid capacity to ensure cost-effective and reliable freight operations. However, the lack of a standardized ownership and service model has led to a fragmented approach—where commercial vehicle operators may invest in, own, and maintain both vehicle/batteries and charging/energy infrastructure. This disconnect may exclude energy service providers from the equation, forcing fleet operators to explore ‘behind-the-fence’ energy solutions that increase capital investment, operational downtime, overhead costs, and, in some cases, net carbon emissions. To address these issues, this study introduces OR-AGENT (Optimal Regional Architecture Generation for Efficient National Transport), a comprehensive modeling framework that integrates powertrain architectures, charging infrastructures, and energy backbone systems into a cohesive strategy. In this paper, OR-AGENT is applied to develop an interconnected systems architecture for energy efficiency and resiliency enhancement of heavy-duty drayage vehicles at the Port of Savannah, GA. This framework showcases an interconnected systems approach to electrifying heavy-duty drayage vehicles at the Port of Savannah, GA. The study assessed BEVs with 400–1200 kWh battery capacities, accounting for seasonal variations in weather and freight routing. A diverse charging mix (150 kW–1250 kW) was evaluated alongside grid capacity constraints, cost, and carbon intensity analysis, leading to the development of a strategic microgrid/Distributed Energy Resources (DER) deployment architecture to ensure a reliable and sustainable transition. However, the findings also highlight the need for alternative zero-emission solutions for remaining trips, such as larger batteries, electrified roadways, hydrogen powertrains, or net-zero emission fuels. In conclusion, the findings are incorporated into a Total Cost of Ownership (TCO) model to identify optimal architectures for an interconnected electrified ecosystem.

Commercial vehicles↗

DOE OSTI2016

Synchronization of Lienard-Type Oscillators in Uniform Electrical Networks

This paper presents a condition for global asymptotic synchronization of Lienard-type nonlinear oscillators in uniform LTI electrical networks with series R-L circuits modeling interconnections. By uniform electrical networks, we mean that the per-unit-length impedances are identical for the interconnecting lines. We derive conditions for global asymptotic synchronization for a particular feedback architecture where the derivative of the oscillator output current supplements the innate current feedback induced by simply interconnecting the oscillator to the network. Our proof leverages a coordinate transformation to a set of differential coordinates that emphasizes signal differences and the particular form of feedback permits the formulation of a quadratic Lyapunov function for this class of networks. This approach is particularly interesting since synchronization conditions are difficult to obtain by means of quadratic Lyapunov functions when only current feedback is used and for networks composed of series R-L circuits. Our synchronization condition depends on the algebraic connectivity of the underlying network, and reiterates the conventional wisdom from Lyapunov- and passivity-based arguments that strong coupling is required to ensure synchronization.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2023

Finding Your Niche: An Evolutionary Approach to HPC Topologies

Traditional interconnection network design approaches focus on building general network topologies by optimizing the bisection bandwidth or minimizing the network’s diameter to reduce the maximum distance between any two nodes, thus amortizing the overall execution time of the HPC workloads. While such network topologies may accommodate a wide variety of applications in general, this may result in sub-optimal performance for many frequently-executed or dynamic workloads. In this paper, instead of focusing on designing an all-encompassing, general-purpose network topology, we develop a methodology to design customized network interconnects, evolved by “finding” the optimal topologies for a particular target workload given by its communication and contention profiles. To this end, we implement a Genetic Algorithm (GA)-based approach for network topology design tailored to improve the overall execution time of a particular workload of interest. We conducted extensive experiments with well-known motifs in physics-based workloads (Sweep3D and FFT), as well as with a representative graph application (MiniVite), using the well-known Structural Simulation Toolkit (SST) Macroscale Element Library (SST/macro) simulator for network interconnect evaluation. We demonstrate that our genetic algorithm-based approach is robust enough to find the underlying optimal topology of a particular workload.

network interconnects, graph search, meta-heuristi↗

DOE OSTI2017

Contact Drying of Printed Sinterable-Silver Paste

We report that drying of stencil-, screen-, or dispense-printed paste is a crucial, yet taken-for-granted, presintering step for sinterable-silver (SS) interconnect processing and ultimately its reliability. If the paste’s solvent is not sufficiently removed during drying, then entrapped gas can result, and that leads to the formation of thermal-, strength-, and reliability-limiting defects in the later-sintered interconnect layer. Presently advocated drying strategies for wet silver paste cause either a limit of associated size or area or require pressure assistance during subsequent sintering. Alternatively, open-face contact drying (OContDry) from contact heating or conductive heating (a method used in industrial processes) offers the potential to overcome those limitations with SS paste. However, satisfactory strength of its final sintered structure must be proven prior to any potential adoption. In this paper, the achievement of a combination of relatively large shear failure stress with low scatter for OContDry SS was demonstrated. Lastly, this is significant because OContDry enables greater processing versatility with SS interconnects and several other advantages too.

36 MATERIALS SCIENCE↗

DOE OSTI2016

Modeling a Million-Node Slim Fly Network Using Parallel Discrete-Event Simulation

As supercomputers close in on exascale performance, the increased number of processors and processing power translates to an increased demand on the underlying network interconnect. The Slim Fly network topology, a new lowdiameter and low-latency interconnection network, is gaining interest as one possible solution for next-generation supercomputing interconnect systems. In this paper, we present a high-fidelity Slim Fly it-level model leveraging the Rensselaer Optimistic Simulation System (ROSS) and Co-Design of Exascale Storage (CODES) frameworks. We validate our Slim Fly model with the Kathareios et al. Slim Fly model results provided at moderately sized network scales. We further scale the model size up to n unprecedented 1 million compute nodes; and through visualization of network simulation metrics such as link bandwidth, packet latency, and port occupancy, we get an insight into the network behavior at the million-node scale. We also show linear strong scaling of the Slim Fly model on an Intel cluster achieving a peak event rate of 36 million events per second using 128 MPI tasks to process 7 billion events. Detailed analysis of the underlying discrete-event simulation performance shows that a million-node Slim Fly model simulation can execute in 198 seconds on the Intel cluster.

interconnection networks↗

DOE OSTI2018

Modeling Large-Scale Slim Fly Networks Using Parallel Discrete-Event Simulation

As supercomputers approach exascale performance, the increased number of processors translates to an increased demand on the underlying network interconnect. We present that the slim fly network topology, a new low-diameter, low-latency, and low-cost interconnection network, is gaining interest as one possible solution for next-generation supercomputing interconnect systems. In this article, we present a high-fidelity slim fly packet-level model leveraging the Rensselaer Optimistic Simulation System (ROSS) and Co-Design of Exascale Storage (CODES) frameworks. We validate the model with published work before scaling the network size up to an unprecedented 1 million compute nodes and confirming that the slim fly observes peak network throughput at extreme scale. In addition to synthetic workloads, we evaluate large-scale slim fly models with real communication workloads from applications in the Design Forward program with over 110,000 MPI processes. We show strong scaling of the slim fly model on an Intel cluster achieving a peak network packet transfer rate of 2.3 million packets per second and processing over 7 billion discrete events using 128 MPI tasks. Enabled by the strong performance capabilities of the model, we perform a detailed application trace and routing protocol performance study. Lastly, through analysis of metrics such as packet latency, hop count, and congestion, we find that the slim fly network is able to leverage simple minimal routing and achieve the same performance as more complex adaptive routing for tested DOE benchmark applications.

97 MATHEMATICS AND COMPUTING↗