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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 865 records · Page 48
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Performance evaluation of the JPL interim digital SAR processor

The performance of the Interim Digital SAR Processor (IDP) was evaluated. The IDP processor was originally developed for experimental processing of digital SEASAT SAR data. One phase of the system upgrade which features parallel processing in three peripheral array processors, automated estimation for Doppler parameters, and unsupervised image pixel location determination and registration was executed. The method to compensate for the target range curvature effect was improved. A four point interpolation scheme is implemented to replace the nearest neighbor scheme used in the original IDP. The processor still maintains its fast throughput speed. The current performance and capability of the processing modes now available on the IDP system are updated.

Wu, C.↗
NASA NTRS2006

Non Radiation Hardened Microprocessors in Spaced Based Remote Sensing Systems

The CALIPSO (Cloud-Aerosol Lidar and Infrared Pathfinder Satellite Observations) mission is a comprehensive suite of active and passive sensors including a 20Hz 230mj Nd:YAG lidar, a visible wavelength Earth-looking camera and an imaging infrared radiometer. CALIPSO flies in formation with the Earth Observing System Post-Meridian (EOS PM) train, provides continuous, near-simultaneous measurements and is a planned 3 year mission. CALIPSO was launched into a 98 degree sun synchronous Earth orbit in April of 2006 to study clouds and aerosols and acquires over 5 gigabytes of data every 24 hours. The ground track of one CALIPSO orbit as well as high and low intensity South Atlantic Anomaly outlines is shown. CALIPSO passes through the SAA several times each day. Spaced based remote sensing systems that include multiple instruments and/or instruments such as lidar generate large volumes of data and require robust real-time hardware and software mechanisms and high throughput processors. Due to onboard storage restrictions and telemetry downlink limitations these systems must pre-process and reduce the data before sending it to the ground. This onboard processing and realtime requirement load may mean that newer more powerful processors are needed even though acceptable radiation-hardened versions have not yet been released. CALIPSO's single board computer payload controller processor is actually a set of four (4) voting non-radiation hardened COTS Power PC 603r's built on a single width VME card by General Dynamics Advanced Information Systems (GDAIS). Significant radiation concerns for CALIPSO and other Low Earth Orbit (LEO) satellites include the South Atlantic Anomaly (SAA), the north and south poles and strong solar events. Over much of South America and extending into the South Atlantic Ocean the Van Allen radiation belts dip to just 200-800km and spacecraft entering this area are subjected to high energy protons and experience higher than normal Single Event Upset (SEU) and Single Event Latch-up (SEL) rates. Although less significant, spacecraft flying in the area around the poles experience similar upsets. Finally, powerful solar proton events in the range of 10MeV/10pfu to 100MeV/1pfu as are forecasted and tracked by NOAA's Space Environment Center in Colorado can result in Single Event Upset (SEU), Single Event Latch-up (SEL) and permanent failures such as Single Event Gate Rupture (SEGR) in some technologies. (Galactic Cosmic Rays (GCRs) are another source, especially for gate rupture) CALIPSO mitigates common radiation concerns in its data handling through the use of redundant processors, radiation-hardened Application Specific Integrated Circuits (ASIC), hardware-based Error Detection and Correction (EDAC), processor and memory scrubbing, redundant boot code and mirrored files. After presenting a system overview this paper will expand on each of these strategies. Where applicable, related on-orbit data collected since the CALIPSO initial boot on May 4, 2006 will be noted.

Decoursey, Robert J.↗
DOE OSTI2017

Real-Time Fine Grained Occupancy Estimation Using Depth Sensors on ARM Embedded Platforms

Occupancy estimation is an important primitive for a wide range of applications including building energy efficiency, safety, and security. In this paper, we explore the potential of using depth sensors to detect, estimate, identify, and track occupants in buildings. While depth sensors have been widely used for human detection and gesture recognition, computer vision algorithms are typically run on a powerful computer like XBOX or Intel R CoreTM i7 processor. In this work, we develop a prototype system called FORK using off-the-shelf components that performs the entire depth data processing on a cheaper and low power ARM processor in real-time. As ARM processors are extremely weak in running computer vision algorithms, FORK is designed to detect humans and track them in a very efficient way by leveraging a novel lightweight model based approach instead of traditional approaches based on histogram of oriented gradients (HOG) features. Unlike other camera based approaches, FORK is much less privacy invasive (even if the sensor is compromised). Based on a complete implementation, real-world deployment, and extensive evaluation at realistic scenarios, we observe that FORK achieves over 99% accuracy in real-time (4-9 FPS) in occupancy estimation.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2021

Transient recovery problem in acoustics: A multichannel model-based deconvolution approach

Critical acoustical systems operating in complex environments contaminated with disturbances and noise offer an extreme challenge when excited by out-of-the-ordinary, impulsive, transient events that can be undetected and seriously affect their overall performance. Transient impulse excitations must be detected, extracted, and evaluated to determine any potential system damage that could have been imposed; therefore, the problem of recovering the excitation in an uncertain measurement environment becomes one of multichannel deconvolution. Recovering a transient and its initial energy has not been solved satisfactorily, especially when the measurement has been truncated and only a small segment of response data is available. The development of multichannel deconvolution techniques for both complete and incomplete excitation data is discussed, employing a model-based approach based on the state-space representation of an identified acoustical system coupled to a forward modeling solution and a Kalman-type processor for enhancement and extraction. In conclusion, synthesized data are utilized to assess the feasibility of the various approaches, demonstrating that reasonable performance can be achieved even in noisy environments.

42 ENGINEERING↗
DOE OSTI2021

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a customdesigned chip to receive theAddress in Real Time (ART) signals from theVMMfront-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. Furthermore, after four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1987

Life sciences flight experiments microcomputer

A promising microcomputer configuration for the Spacelab Life Sciences Lab. Equipment inventory consists of multiple processors. One processor's use is reserved, with additional processors dedicated to real time input and output operations. A simple form of such a configuration, with a processor board for analog to digital conversion and another processor board for digital to analog conversion, was studied. The system used digital parallel data lines between the boards, operating independently of the system bus. Good performance of individual components was demonstrated: the analog to digital converter was at over 10,000 samples per second. The combination of the data transfer between boards with the input or output functions on each board slowed performance, with a maximum throughput of 2800 to 2900 analog samples per second. Any of several techniques, such as use of the system bus for data transfer or the addition of direct memory access hardware to the processor boards, should give significantly improved performance.

Bartram, Peter N.↗
NASA NTRS1988

An expert system for a distributed real-time trainer

The problem addressed by this expert system concerns the expansion of capability of a Real Time Trainer for the Spacelab flight crew. As requirements for more models or fidelity are placed upon the system, expansion is necessary. The simulator can be expanded using a larger processor or by going to a distributed system and expand by adding additional processors. The distributed system is preferable because it is more economical and can be expanded in a more incremental manner. An expert system was developed to evaluate modeling and timing capability within a real time training simulator. The expert system is based upon a distributed configuration. Components of the modeled system are control tasks, network tasks, emulator tasks, processors, displays, and a network. The distributed module expert system (DMES) allows the configuring of processors, tasks, display use, keyboard use, and selection of alternate methods to update the data buffer. Modules can be defined with execution occurring in a specific processor on a network. The system consists of a knowledge front end editor to interactively generate or update the knowledge base, an inference engine, a display module, and a recording module.

Purinton, Steven C.↗
DOE OSTI2022

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗
DOE OSTI2017

Computer systems and methods for the query and visualization multidimensional databases

A method of generating a data visualization is performed at a computer having a display, one or more processors, and memory. The memory stores one or more programs for execution by the one or more processors. The process receives user specification of a plurality of characteristics of a data visualization. The data visualization is based on data from a multidimensional database. The characteristics specify at least x-position and y-position of data marks corresponding to tuples of data retrieved from the database. The process generates a data visualization according to the specified plurality of characteristics. The data visualization has an x-axis defined based on data for one or more first fields from the database that specify x-position of the data marks and the data visualization has a y-axis defined based on data for one or more second fields from the database that specify y-position of the data marks.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1992

A real time data acquisition system using the MIL-STD-1553B bus

A flight digital data acquisition system that uses the MIL-STD-1553B bus for transmission of data to a host computer for control law processing is described. The instrument, the Remote Interface Unit (RIU), can accommodate up to 16 input channels and eight output channels. The RIU employs a digital signal processor to perform local digital filtering before sending data to the host. The system allows flexible sensor and actuator data organization to facilitate quick control law computations on the host computer. The instrument can also run simple control laws autonomously without host intervention. The RIU and host computer together have replaced a similar larger, ground minicomputer system with favorable results.

Peri, Frank, Jr.↗
NASA NTRS2007

Miniature Intelligent Sensor Module

An electronic unit denoted the Miniature Intelligent Sensor Module performs sensor-signal-conditioning functions and local processing of sensor data. The unit includes four channels of analog input/output circuitry, a processor, volatile and nonvolatile memory, and two Ethernet communication ports, all housed in a weathertight enclosure. The unit accepts AC or DC power. The analog inputs provide programmable gain, offset, and filtering as well as shunt calibration and auto-zeroing. Analog outputs include sine, square, and triangular waves having programmable frequencies and amplitudes, as well as programmable amplitude DC. One innovative aspect of the design of this unit is the integration of a relatively powerful processor and large amount of memory along with the sensor-signalconditioning circuitry so that sophisticated computer programs can be used to acquire and analyze sensor data and estimate and track the health of the overall sensor-data-acquisition system of which the unit is a part. The unit includes calibration, zeroing, and signalfeedback circuitry to facilitate health monitoring. The processor is also integrated with programmable logic circuitry in such a manner as to simplify and enhance acquisition of data and generation of analog outputs. A notable unique feature of the unit is a cold-junction compensation circuit in the back shell of a sensor connector. This circuit makes it possible to use Ktype thermocouples without compromising a housing seal. Replicas of this unit may prove useful in industrial and manufacturing settings - especially in such large outdoor facilities as refineries. Two features can be expected to simplify installation: the weathertight housings should make it possible to mount the units near sensors, and the Ethernet communication capability of the units should facilitate establishment of communication connections for the units.

Beech, Russell S.↗
NASA NTRS1984

Optical Kalman filtering for missile guidance

Optical systolic array processors constitute a powerful and general-purpose set of optical architectures with high computational rates. In this paper, Kalman filtering, a novel application for these architectures, is investigated. All required operations are detailed; their realization by optical and special-purpose analog electronics are specified; and the processing time of the system is quantified. The specific Kalman filter application chosen is for an air-to-air missile guidance controller. The architecture realized in this paper meets the design goal of a fully adaptive Kalman filter which processes a measurement every 1 msec. The vital issue of flow and pipelining of data and operations in a systolic array processor is addressed. The approach is sufficiently general and can be realized on an optical or digital systolic array processor.

Casasent, D.↗
NASA NTRS2012

From EXOSAT to the High Energy Astrophysics Science Archive (HEASARC): X-ray Astronomy Comes of Age

In May 1983 the European Space Agency launched EXOSAT, its first X-ray astronomy observatory. Even though it lasted only 3 short years, this mission brought not only new capabilities that resulted in unexpected discoveries, but also a pioneering approach to operations and archiving that changed X-ray astronomy from observations led by small instrument teams, to an observatory approach open to the entire community through a guest observer program. The community use of the observatory was supported by a small dedicated team of scientists, the precursor to the data center activities created to support e.g. Chandra and XMM-Newton. The new science capabilities of EX OS AT included a 90 hr highly eccentric high earth orbit that allow unprecedented continuous coverage of sources as well as direct communication with the satellite that allowed real time decisions to respond to unexpected events through targets of opportunity. The advantages of this orbit demonstrated by EXOSAT resulted in Chandra and XMM-Newton selecting similar orbits. The three instruments on board the EXOSAT observatory were complementary, designed to give complete coverage over a wide energy band pass of 0.05-50 keY. An onboard processor could be programmed to give multiple data modes that could be optimized in response to science discoveries: These new capabilities resulted in many new discoveries including the first comprehensive study of AGN variability, new orbital periods in X-ray binaries and cataclysmic variables, new black holes, quasi-periodic oscillations from neutron stars and black holes and broad band X-ray spectroscopy. The EXOSAT team generated a well-organized database accessible worldwide over the nascent internet, allowing remote selection of data products, making samples and undertaking surveys from the data. The HEASARC was established by NASA at Goddard Space Flight Center in 1990 as the repository of NASA X-ray and Gamma-ray data. The proven EXOSAT database system became the core of the HEASARC infrastructure. The HEASARC pioneered many concepts now taken for granted including standardized formats using FITS files, restoring data from earlier missions, multi-mission analysis tools and a searchable archive over the world wide web.

White, Nicholas E.↗
NASA NTRS1982

On nonlinear finite element analysis in single-, multi- and parallel-processors

Numerical solution of nonlinear equilibrium problems of structures by means of Newton-Raphson type iterations is reviewed. Each step of the iteration is shown to correspond to the solution of a linear problem, therefore the feasibility of the finite element method for nonlinear analysis is established. Organization and flow of data for various types of digital computers, such as single-processor/single-level memory, single-processor/two-level-memory, vector-processor/two-level-memory, and parallel-processors, with and without sub-structuring (i.e. partitioning) are given. The effect of the relative costs of computation, memory and data transfer on substructuring is shown. The idea of assigning comparable size substructures to parallel processors is exploited. Under Cholesky type factorization schemes, the efficiency of parallel processing is shown to decrease due to the occasional shared data, just as that due to the shared facilities.

Utku, S.↗
NASA NTRS1988

Development of an 8000 bps voice codec for AvSat

Air-mobile speech communication applications share robustness and noise immunity requirements with other mobile applications. The quality requirements are stringent, especially in the cockpit where air safety is involved. Based on these considerations, a decision was made to test an intermediate data rate such as 8.0 and 9.6 kb/s as proven technologies. A number of vocoders and codec technologies were investigated at rates ranging from 2.4 kb/s up to and including 9.6 kb/s. The proven vocoders operating at 2.4 and 4.8 kb/s lacked the noise immunity or the robustness to operate reliably in a cabin noise environment. One very attractive alternative approach was Spectrally Encoded Residual Excited LPC (SE-RELP) which is used in a multi-rate voice processor (MRP) developed at the Naval Research Lab (NRL). The MRP uses SE-RELP at rates of 9.6 and 16 kb/s. The 9.6 kb/s rate can be lowered to 8.0 kb/s without loss of information by modifying the frame. An 8.0 kb/s vocoder was developed using SE-RELP as a demonstrator and testbed. This demonstrator is implemented in real time using two Compaq 2 portable computers, each equipped with an ARIEL DSP016 Data Acquisition Processor.

Clark, Joseph F.↗
NASA NTRS1988

Accelerated convergence for synchronous approximate agreement

The protocol for synchronous approximate agreement presented by Dolev et. al. exhibits the undesirable property that a faulty processor, by the dissemination of a value arbitrarily far removed from the values held by good processors, may delay the termination of the protocol by an arbitrary amount of time. Such behavior is clearly undesirable in a fault tolerant dynamic system subject to hard real-time constraints. A mechanism is presented by which editing data suspected of being from Byzantine-failed processors can lead to quicker, predictable, convergence to an agreement value. Under specific assumptions about the nature of values transmitted by failed processors relative to those transmitted by good processors, a Monte Carlo simulation is presented whose qualitative results illustrate the trade-off between accelerated convergence and the accuracy of the value agreed upon.

Kearns, J. P.↗
DOE OSTI2019

Design and Evaluation of the LAr Trigger Digitizer Board in the ATLAS Phase-I Upgrade

The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) calorimeters will be installed during the second long shutdown of the Large Hadron Collider (LHC) in 2019-2020 which will enable enhanced instantaneous luminosities during LHC Run 3 from 2021 through 2023. In this trigger upgrade, so-called supercells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the Level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will process and digitize up to 320 channels of supercell signals, and transmit them via 40 fiber optical links to the back end where the data are further processed and transmitted to the trigger processors. Five pairs of bidirectional GBT links are used for slow control and monitoring between LTDB and the Front-End LInk eXchange (FELIX) in the ATLAS Trigger and Data Acquisition (TDAQ) system. Here, the LTDB also outputs 64 summed analog legacy signals to the current Tower Builder Board via a new baseplane. A test system for the production of 124 LTDBs has been developed, supporting configuration and calibration of all ASICs

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

VTK-m: Visualization for the Exascale Era and Beyond

A recent trend in modern high-performance computing is the increasing use of hybrid architectures, where the vast majority of performance comes from accelerators. Modern accelerators are based on Graphics Processing Units (GPU) that contain many low power cores that in their aggregate provides an extremely high computation rate. Current and future CPU processors are requiring more explicit parallelism as each successive version of the hardware packs in more cores, and technologies like hyperthreading and vector operations require even more parallel processing to leverage each core’s full potential. As an example, the Frontier supercomputer installed at Oak Ridge National Laboratories recently hit a record breaking 1.1 exaflops1 on the LINPACK HPC benchmark [Shoemaker 2022]. The system contains 37632 AMD MI250x GPUs which requires more than half a billion threads to keep the system fully utilized [Khizeran 2022].VTK-m is a toolkit of scientific visualization algorithms for these emerging processor architectures. VTK-m supports the fine-grained concurrency for data analysis and visualization algorithms required to drive extreme scale computing by providing abstract models for data and execution that can be applied to a variety of algorithms across many different processor architectures.

Bolstad, Mark↗