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At least 865 records · Page 48

The instrumental principles of MST radars and incoherent scatter radars and the configuration of radar system hardware

The principle of pulse modulation used in the case of coherent scatter radars (MST radars) is discussed. Coherent detection and the corresponding system configuration is delineated. Antenna requirements and design are outlined and the phase-coherent transmitter/receiver system is described. Transmit/receive duplexers, transmitters, receivers, and quadrature detectors are explained. The radar controller, integrator, decoder and correlator design as well as the data transfer and the control and monitoring by the host computer are delineated. Typical operation parameters of some well-known radars are summarized.

Roettger, Juergen↗

Quantum-classical tradeoffs and multi-controlled quantum gate decompositions in variational algorithms

The computational capabilities of near-term quantum computers are limited by the noisy execution of gate operations and a limited number of physical qubits. Hybrid variational algorithms are well-suited to near-term quantum devices because they allow for a wide range of tradeoffs between the amount of quantum and classical resources used to solve a problem. This paper investigates tradeoffs available at both the algorithmic and hardware levels by studying a specific case – applying the Quantum Approximate Optimization Algorithm (QAOA) to instances of the Maximum Independent Set (MIS) problem. We consider three variants of the QAOA which offer different tradeoffs at the algorithmic level in terms of their required number of classical parameters, quantum gates, and iterations of classical optimization needed. Since MIS is a constrained combinatorial optimization problem, the QAOA must respect the problem constraints. This can be accomplished by using many multi-controlled gate operations which must be decomposed into gates executable by the target hardware. We study the tradeoffs available at this hardware level, combining the gate fidelities and decomposition efficiencies of different native gate sets into a single metric called the gate decomposition cost .

Tomesh, Teague↗

SIRU development. Volume 3: Software description and program documentation

The development and initial evaluation of a strapdown inertial reference unit (SIRU) system are discussed. The SIRU configuration is a modular inertial subsystem with hardware and software features that achieve fault tolerant operational capabilities. The SIRU redundant hardware design is formulated about a six gyro and six accelerometer instrument module package. The six axes array provides redundant independent sensing and the symmetry enables the formulation of an optimal software redundant data processing structure with self-contained fault detection and isolation (FDI) capabilities. The basic SIRU software coding system used in the DDP-516 computer is documented.

Oehrle, J.↗

Digital data processing system dynamic loading analysis

Simulation and analysis of the Space Shuttle Orbiter Digital Data Processing System (DDPS) are reported. The mated flight and postseparation flight phases of the space shuttle's approach and landing test configuration were modeled utilizing the Information Management System Interpretative Model (IMSIM) in a computerized simulation modeling of the ALT hardware, software, and workload. System requirements simulated for the ALT configuration were defined. Sensitivity analyses determined areas of potential data flow problems in DDPS operation. Based on the defined system requirements and the sensitivity analyses, a test design is described for adapting, parameterizing, and executing the IMSIM. Varying load and stress conditions for the model execution are given. The analyses of the computer simulation runs were documented as results, conclusions, and recommendations for DDPS improvements.

Lagas, J. J.↗

International Space Station environmental control and life support system. Phase 3: Water Recovery Test Stage 9

A test has been completed at NASA's Marshall Space Flight Center (MSFC) to evaluate the latest water recovery system design for the United States On-Orbit Segment (USOS) of the International Space Station (ISS) with higher fidelity hardware and integration than has been achieved in previous Water Recovery Test (WRT) Stages. This test is referred to as WRT Stage 9. Potable and urine processing assemblies were integrated with end-use equipment and operated for 116 days. The overall integrated configuration of the test system included a single water recovery loop that was automated and controlled from a central computer. This report summarizes the test objectives, system design, test activities and protocols, significant results, anomalies and lessons learned throughout the WRT Stage 9.

D L Carter↗

Development of a Telescoping Vaned Exhaust Nozzle for the ASTOVL LiftFan(Trademark) Application

A discussion on the development of a Telescoping, Vaned, Exhaust Nozzle (TEVEN) is presented. This nozzle was challenged to meet the thrust vectoring requirements of an Advanced Short Takeoff and Vertical Landing (ASTOVL) aircraft. The nozzle underwent a development process from concepts to detail design using computational flow analyses and from subscale performance verification tests to full-scale hardware design. The LiftFan(Trademark) nozzle is capable of providing a pitch vector range of about 80 degrees from up to 20 degrees forward to 60 degrees aft. In addition, a set of post exit yaw doors provide +/- 10 degrees yaw while maintaining a relatively high performance at all operating conditions. Further, the nozzle is axially compact, to be stowable in very short length (LJD less than 0.3), while efficiently converging the upstream nozzle flow from an annular cross section to a "D" shape at the nozzle exit. The discussion includes a review of various nozzle concepts, viscous flow analyses, and results from 1/3 scale nozzle model tests conducted at NASA LeRC Powered Lift Facility (PLF) in 1994.

Sokhey, Jack S.↗

General Aviation Data Framework

The Flight Research Services Directorate at the NASA Langley Research Center (LaRC) provides development and operations services associated with three general aviation (GA) aircraft used for research experiments. The GA aircraft includes a Cessna 206X Stationair, a Lancair Colombia 300X, and a Cirrus SR22X. Since 2004, the GA Data Framework software was designed and implemented to gather data from a varying set of hardware and software sources as well as enable transfer of the data to other computers or devices. The key requirements for the GA Data Framework software include platform independence, the ability to reuse the framework for different projects without changing the framework code, graphics display capabilities, and the ability to vary the interfaces and their performance. Data received from the various devices is stored in shared memory. This paper concentrates on the object oriented software design patterns within the General Aviation Data Framework, and how they enable the construction of project specific software without changing the base classes. The issues of platform independence and multi-threading which enable interfaces to run at different frame rates are also discussed in this paper.

Blount, Elaine M.↗

Protonic nickelate device networks for spatiotemporal neuromorphic computing

Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging, as most neuromorphic devices emulate only isolated neuron- or synapse-like functions. Here we introduce an integrated neuromorphic computing platform in which both nonlinear spatiotemporal processing and programmable memory are realized within a single perovskite nickelate material system. By engineering symmetric and asymmetric hydrogenated NdNiO 3 junction devices on the same wafer, we combine ultrafast, proton-mediated transient dynamics with stable multilevel resistance states. Networks of symmetric NdNiO 3 junctions exhibit emergent spatial interactions mediated by proton redistribution, while each node simultaneously provides short-term temporal memory, enabling nanosecond-scale operation with an energy cost of ~0.2 nJ per input. When interfaced with asymmetric output units serving as reconfigurable long-term weights, these networks allow both feature transformation and linear classification in the same material system. Leveraging these emergent interactions, the platform enables real-time pattern recognition and achieves high accuracy in spoken digit classification and early seizure detection, outperforming temporal-only or uncoupled architectures. These results position protonic nickelates as a compact, energy-efficient, CMOS-compatible platform that integrates processing and memory for scalable intelligent hardware.

Electrical and electronic engineering↗

Measurement and Computation of Supersonic Flow in a Lobed Diffuser-Mixer for Trapped Vortex Combustors

The trapped vortex combustor (TVC) pioneered by Air Force Research Laboratories (AFRL) is under consideration as an alternative to conventional gas turbine combustors. The TVC has demonstrated excellent operational characteristics such as high combustion efficiency, low NO(x) emissions, effective flame stabilization, excellent high-altitude relight capability, and operation in the lean-burn or rich burn-quick quench-lean burn (RQL) modes of combustion. It also has excellent potential for lowering the engine combustor weight. This performance at low to moderate combustor mach numbers has stimulated interest in its ability to operate at higher combustion mach number, and for aerospace, this implies potentially higher flight mach numbers. To this end, a lobed diffuser-mixer that enhances the fuel-air mixing in the TVC combustor core was designed and evaluated, with special attention paid to the potential shock system entering the combustor core. For the present investigation, the lobed diffuser-mixer combustor rig is in a full annular configuration featuring sixfold symmetry among the lobes, symmetry within each lobe, and plain parallel, symmetric incident flow. During hardware cold-flow testing, significant discrepancies were found between computed and measured values for the pitot-probe-averaged static pressure profiles at the lobe exit plane. Computational fluid dynamics (CFD) simulations were initiated to determine whether the static pressure probe was causing high local flow-field disturbances in the supersonic flow exiting the diffuser-mixer and whether shock wave impingement on the pitot probe tip, pressure ports, or surface was the cause of the discrepancies. Simulations were performed with and without the pitot probe present in the modeling. A comparison of static pressure profiles without the probe showed that static pressure was off by nearly a factor of 2 over much of the radial profile, even when taking into account potential axial displacement of the probe by up to 0.25 in. (0.64 cm). Including the pitot probe in the CFD modeling and data interpretation lead to good agreement between measurement and prediction. Graphical inspection of the results showed that the shock waves impinging on the probe surface were highly nonuniform, with static pressure varying circumferentially among the pressure ports by over 10 percent in some cases. As part of the measurement methodology, such measurements should be routinely supplemented with CFD analyses that include the pitot probe as part of the flow-path geometry.

Brankovic, Andreja↗

NASA Operational Simulator for Small Satellites: Tools for Software Based Validation and Verification of Small Satellites

The NASA Operational Simulator for Small Satellites (NOS3) is a suite of tools to aid in areas such as software development, integration test (IT), mission operations training, verification and validation (VV), and software systems check-out. NOS3 provides a software development environment, a multi-target build system, an operator interface-ground station, dynamics and environment simulations, and software-based hardware models. NOS3 enables the development of flight software (FSW) early in the project life cycle, when access to hardware is typically not available. For small satellites there are extensive lead times on many of the commercial-off-the-shelf (COTS) components as well as limited funding for engineering test units (ETU). Considering the difficulty of providing a hardware test-bed to each developer tester, hardware models are modeled based upon characteristic data or manufacturers data sheets for each individual component. The fidelity of each hardware models is such that FSW executes unaware that physical hardware is not present. This allows binaries to be compiled for both the simulation environment, and the flight computer, without changing the FSW source code. For hardware models that provide data dependent on the environment, such as a GPS receiver or magnetometer, an open-source tool from NASA GSFC (42 Spacecraft Simulation) is used to provide the necessary data. The underlying infrastructure used to transfer messages between FSW and the hardware models can also be used to monitor, intercept, and inject messages, which has proven to be beneficial for VV of larger missions such as James Webb Space Telescope (JWST). As hardware is procured, drivers can be added to the environment to enable hardware-in-the-loop (HWIL) testing. When strict time synchronization is not vital, any number of combinations of hardware components and software-based models can be tested. The open-source operator interface used in NOS3 is COSMOS from Ball Aerospace. For testing, plug-ins are implemented in COSMOS to control the NOS3 simulations, while the command and telemetry tools available in COSMOS are used to communicate with FSW. NOS3 is actively being used for FSW development and component testing of the Simulation-to-Flight 1 (STF-1) CubeSat. As NOS3 matures, hardware models have been added for common CubeSat components such as Novatel GPS receivers, ClydeSpace electrical power systems and batteries, ISISpace antenna systems, etc. In the future, NASA IVV plans to distribute NOS3 to other CubeSat developers and release the suite to the open-source community.

Verification↗

Direct modeling parameter signature analysis and failure mode prediction of physical systems using hybrid computer optimization

High speed automated identification and design of dynamic systems, both linear and nonlinear, are discussed. Special emphasis is placed on developing hardware and techniques which are applicable to practical problems. The basic modeling experiment and new results are described. Using the improvements developed successful identification of several systems, including a physical example as well as simulated systems, was obtained. The advantages of parameter signature analysis over signal signature analysis in go-no go testing of operational systems were demonstrated. The feasibility of using these ideas in failure mode prediction in operating systems was also investigated. An improved digital controlled nonlinear function generator was developed, de-bugged, and completely documented.

Drake, R. L.↗

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗

Docker Containers for MCNP ® Development

Containers are a revolutionary technology in software development and deployment that provides a lightweight, portable environment for ensuring consistency across multiple computing environments. In anticipation of the MCNP 6.3.1 release, two Docker container images have been released on DockerHub for general use. The MCNP source code is not included in the images, and users are still required to obtain it through RSICC. The images produced by Docker are compliant with the OCI (Open Container Initiative) standards, ensuring compatibility with other container engines such as Podman or Kubernetes’ CRI-O. Initially, the images are stored under the author’s personal space on DockerHub (docker.io/azukaitis), but they will be relocated to a dedicated MCNP group space once approved. In the future, they will also be available through the registry feature of the https://github.com/lanl/mcnp-containers project. The use of Docker provides a pre-configured environment for building and running MCNP, ensuring reproducibility of results across various host architectures. This significantly improves consistency when running MCNP on different systems. Notably, executables and installers from the Docker images have successfully passed the MCNP development branch testing suite on x86-64 architectures, including Windows, macOS, and Linux operating systems. Furthermore, testing has demonstrated compatibility with macOS Docker in emulation mode on the latest Apple Mac M2 Ultra hardware, ensuring robust support even on the latest platforms. In this document, we will provide a step-by-step guide to using the Docker images across multiple platforms. Additionally, we will present performance numbers for building and running the MCNP test suite.

97 MATHEMATICS AND COMPUTING↗

Visual Analytics of Crosstalk in Quantum Hardware

Crosstalk remains a major obstacle to building scalable and fault-tolerant quantum computers. Conventional diagnostic techniques-often based on numerical simulation or statistical modeling-struggle to scale with hardware complexity and offer limited interpretability. In this work, we present a visual analytics framework for diagnosing qubit crosstalk using lightweight, circuit-based models integrated with an interactive user interface. Our approach quantifies correlations between active and idle qubits under parameterized single- and twoqubit operations, enabling detection of both spatial and gateinduced crosstalk. The system incorporates qubit topology and gate performance data to support sector-based exploration and correlation mapping. This tool assists users in identifying correlated error sources, informing qubit placement strategies, and guiding noise-aware circuit design.

Chae, Junghoon [ORNL] (ORCID:0000000206016746)↗

BoBa

BoBa is a C++ software library for working with large matrices, tensors, and tensor decompositions. The library provides tools for dense matrix and tensor operations, tensor decompositions, and tensor decomposition methods that support modern CPU and GPU architectures. It includes portable abstractions for linear algebra, tensor algebra, and multidimensional computation. BoBa is intended for scientific computing applications that involve large multidimensional data sets or high dimensional mathematical models. Its capabilities support tasks such as data compression, linear algebra, efficient numerical computation, and the development of scalable algorithms for heterogeneous hardware. Tutorials, tests, and example applications are included to help users learn and apply the library.

Yao, Jin [Lawrence Livermore National Laboratory (↗

Quantum Workforce Development at Lawrence Livermore National Laboratory

The students applying to LLNL that are interested in quantum computing are being brought up with a universal quantum algorithm experience. The candidates we see have played with Qiskit or the IBM experience, they understand spin dynamics, and a few of them have attended hackathons by Rigetti or another company. These students have all been exposed to universal quantum computing, but not quantum engineering, quantum hardware, or even descriptions of noise. This is in a large part due to the simplified interface in current commercial quantum systems. To broaden the applicant pool, we have begun collaborating with several institutions to train quantum scientists and engineers. We are using the LLNL whitebox approach to testbed access in order to give students a look under the hood of quantum computing operations because that is what we desire in research scientists.

42 ENGINEERING↗

Benchmarking Real-Time Control Platforms Using a Matlab/Simulink Coder with Applications in the Control of DC/AC Switched Power Converters

In the control of DC/AC switched power converters (SPC), one of the most important aspects to be considered is the selection of the real-time control platform. The real-time control platform must be able to meet the high performance efficiency and regulation requirements of the DC/AC SPC, as these typically operate at switching frequencies in the order of kHz to MHz. For this reason, the hardware characteristics of the ADC and PWM, and the processing capacity of the real-time control platform are of vital importance when implementing advanced digital controllers that maintain voltage and current levels within regulatory standards. In this context, we aimed to perform a comparative study of the computation times of different real-time control platforms when implementing different control strategies for DC/AC switched power converters. We also analyzed the impact of the real-time control platforms on the THD of the voltages generated by the DC/AC switched power converters. With the help of this paper, researchers and developers will have criteria to select which real-time control platform to use in real-time control for DC/AC SPC applications.

42 ENGINEERING↗

A time lag study of the vertical motion simulator computer system

A study was performed to evaluate an experimental method to determine time lags in real-time computer systems as the one associated with the Vertical Motion Simulator at Ames Research Center. The approach was to use an ordinary frequency analyzer to measure the phase difference between inputs and outputs of the computer system. The various elements of the program and computational architecture were modeled. Various factors, such as computer frame time and input frequency, were varied so that they were representative of the operational use of the simulator facilities. Experimentally determined results were compared with predictions derived from the simulation models. The results indicate that the frequency analyzer can be readily used to evaluate time lags in systems of this type. Differences between predicted and measured phase values indicate that the hardware and software imparts a time lag of about 5 msec to this facility.

Cleveland, W. B.↗