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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 847 records · Page 47
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Controlling accesses to a branch prediction unit for sequences of fetch groups

An electronic device handles accesses of a branch prediction functional block when executing instructions in program code. The electronic device includes a processor having the branch prediction functional block that provides branch prediction information for control transfer instructions (CTIs) in the program code and a minimum predictor use (MPU) functional block. The MPU functional block determines, based on a record associated with a given fetch group of instructions, that a specified number of subsequent fetch groups of instructions that were previously determined to include no CTIs or conditional CTIs that were not taken are to be fetched for execution in sequence following the given fetch group. The MPU functional block then, when each of the specified number of the subsequent fetch groups is fetched and prepared for execution, prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that subsequent fetch group.

Agrawal, Varun↗
DOE OSTI2021

Improving scalability of electronic structure code for molecular simulations in the presence of environment

A scalable density functional electronic code with Gaussian basis set, called UTEP-NRLMOL, is developed to perform simulations of molecular systems in the presence of the environment with particular attention to the memory requirements. In the electronic structure calculations, the memory and computation time are proportional to the number of atoms. Memory requirements for density functional calculations scale as N*N, where N is the number of atoms. While the recent advances in HPC offer platforms with large numbers of cores, the limited amount of memory available on a given node and poor scalability of the electronic structure codes hinder their efficient usage of these platforms. We have introduced new scaling and parallelization paradigms using MPI-3 shared-memory functionality combined with usage of sparse algebra and storage of matrices in sparse format. This extends the range of applicability of the UTEP-NRLMOL code to large systems over 10,000 atoms, or using up to 67,000 basis functions, and making use of HPC architectures using over 6,000 processors utilizing all available cores. We have also interfaced code with effective fragment potential and polarizable continuum model libraries. The code was used in simulations of several applications which are published in reputed scientific journals.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2021

A Novel Decentralized PWM Interleaving Technique for Ripple Minimization in Series-Stacked DC-DC Converters: Preprint

Cascaded dc-dc converters are commonly used in applications where distributed energy sources or loads are connected to elevated voltage levels for power transfer. In such systems, it is advantageous to minimize the ripple on the bus current and voltage by proper phase shifting of the pulse-width modulation (PWM) pulses among the converters via a method known as interleaving. Existing approaches use either a centralized controller or separate communication lines among the stacked converters to control their relative PWM switch transitions. The key drawbacks are that these methods entail significant wiring, the central controller acts as a single point of failure, and implementation on very large numbers of units is impractical. In this paper, we introduce a decentralized interleaving control (DIC) strategy that acts on local current measurements at every converter and achieves communication-free PWM interleaving among the series-stacked converters. The proposed controller is simple in structure and is shown to converge asymptotically to the interleaved state irrespective of clock drifts among the digital signal processors. Experimental results are provided for a system of five series-connected converters showing a 10 times reduction in the current ripple compared to normal operation.

41 EE - Solar Energy Technologies Office (EE-4S)↗
DOE OSTI2021

Method and apparatus for virtualizing the micro-op cache

Systems, apparatuses, and methods for virtualizing a micro-operation cache are disclosed. A processor includes at least a micro-operation cache, a conventional cache subsystem, a decode unit, and control logic. The decode unit decodes instructions into micro-operations which are then stored in the micro-operation cache. The micro-operation cache has limited capacity for storing micro-operations. When new micro-operations are decoded from pending instructions, existing micro-operations are evicted from the micro-operation cache to make room for the new micro-operations. Rather than being discarded, micro-operations evicted from the micro-operation cache are stored in the conventional cache subsystem. This prevents the original instruction from having to be decoded again on subsequent executions. When the control logic determines that micro-operations for one or more fetched instructions are stored in either the micro-operation cache or the conventional cache subsystem, the control logic causes the decode unit to transition to a reduced-power state.

Kalamatianos, John↗
DOE OSTI2021

Heterogeneous network topology management and control

In one aspect, the present disclosure may provide devices or systems configured to receive indications of geographic areas, each corresponding to distribution networks, and determine whether the distribution networks overlap. The processor(s) may also be configured to receive parameter value(s) obtained by a device within one distribution network at a location within an overlapping area, and cause device(s) within another distribution network to modify operation based on the parameter value(s). In another aspect, the present disclosure may provide devices that include a voltage sensor to measure a voltage of a power distribution network at a power consumption location that corresponds to the device. The device may be configured to provide at least one cable service to the power consumption location via a cable television (CATV) distribution network and output an indication the measured voltage value.

Cruickshank, III, Robert Fraser↗
DOE OSTI2021

Open port sampling interface

A system for sampling a sample material includes a probe which can have an outer probe housing with an open end. A liquid supply conduit within the housing has an outlet positioned to deliver liquid to the open end of the housing. The liquid supply conduit can be connectable to a liquid supply for delivering liquid at a first volumetric flow rate to the open end of the housing. A liquid exhaust conduit within the housing is provided for removing liquid from the open end of the housing. A liquid exhaust system can be provided for removing liquid from the liquid exhaust conduit at a second volumetric flow rate. A droplet dispenser can dispense drops of a sample or a sample-containing solvent into the open end of the housing. A sensor and a processor can be provided to monitor and maintain a liquid dome present at the open end.

Van Berkel, Gary J.↗
DOE OSTI2021

Method of controlling a vehicle to adjust perception system energy usage

A method of controlling a vehicle includes determining a current operating situation of the vehicle, and identifying a subset of a plurality of sensors of the vehicle needed to provide data to enable a vehicle control function for the current operating situation of the vehicle. A remainder of the plurality of sensors is disengaged to reduce electric energy usage by the vehicle while the vehicle is operating in the current operating situation of the vehicle. A sampling rate for the selected subset of sensors may be reduced to further reduce energy usage of the vehicle. Additionally, an energy reduction processing strategy may be implemented to reduce a processor frequency or a voltage of a computing device used to provide the vehicle control function to further reduce energy usage of the vehicle.

Hu, Yuxiao↗
DOE OSTI2021

Reliability processing of remote direct memory access

Methods and systems for monitoring remote transmissions of messages among a plurality of nodes are described. A processing element in a first node may allocate a sequence number to a request to read and/or update data in a second node. The processing element may be different from main processors of the first node. The processing element may send the message and the sequence number to the second node. The processing element may modify a status of the sequence number to an active state, indicating a transmission of the message is pending. The processing element may, in response to a response from the second node, modify the status of the sequence number to an inactive state, indicating a completed transmission of the message. The processing element may, in response to no response from the second node within a time period, resend the message and the sequence number to the second node.

Kumar, Sameer↗
DOE OSTI2021

Toward Performance Portable Programming for Heterogeneous System-on-Chips: Case Study with Qualcomm Snapdragon SoC

Future heterogeneous Domain-Specific System-on-Chips (DSSoC) will be extraordinarily complex in terms of processors, memory hierarchies, and interconnection networks.To manage this complexity, architects, system software designers, and application developers need programming technologies that are flexible, accurate, efficient, and productive. These technologies will need to be as independent of any one specific architecture as is practical, because the sheer dimensionality and scale of the complexity will not allow porting and optimizing applications foreach given DSSoC. To address these issues, we are developing Cosmic Castle, a performance portable programming toolchain for streaming applications on heterogeneous architectures. The primary focus of Cosmic Castle is on enabling efficient and performant code generation through the smart compiler and intelligent runtime system. This paper presents the preliminary evaluation of our ongoing work toward Cosmic Castle. Specifically, we detail our code porting efforts and evaluate various benchmarks on the Qualcomm Snapdragon SoC using tools developed through Cosmic Castle.

Cabrera, Anthony↗
DOE OSTI2021

System and method for focal-plane illuminator/detector (FASID) design for improved graded index lenses

The present disclosure relates to a detector system for imaging an optical signal received by a graded index (GRIN) optical element to account for known variations in a graded index distribution of the GRIN optical element. The detector system incorporates a plurality of optical detector elements configured to receive optical rays received by the GRIN optical element at specific locations on a plane of the GRIN optical element. Ray tracing software is configured to receive and map the optical rays to a plurality of additional specific locations on the plane based on the known variations in the graded index distribution of the GRIN optical element. A processor uses algorithms for diagonalization of a linear system matrix to determine information on both an intensity and an angle of the received optical rays at each one of the plurality of specific locations on the plane.

Bude, Jeffrey Devin↗
DOE OSTI2021

Shareable FPGA compute engine

Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.

Kegel, Andrew G.↗
DOE OSTI2021

System and method for monitoring atomic absorption during a surface modification process

A processing system monitors and/or controls a surface modification process occurring on a substrate within a processing chamber. An optical processing module having a light emission submodule to output a generated light signal and an optical detection submodule to detect a resultant light signal, is connected via fiber optic cables to light illuminating and light receiving components located within the chamber. A processor determines an amount of atomic absorption by an atomic element encountered by a probing beam passing between the illuminating and receiving components, based on the intensity of the generated light signal, the intensity of the received light signal and optionally the spontaneous emission of the atomic element in the absence of illumination by a probing beam. Based on the determined amount, the system derives a plurality of parameters of the modified substrate, their spatial and temporal uniformity, and information about process conditions in the processing chamber.

Atanasoff, George↗
DOE OSTI2021

Two and three-dimensional near infrared subcutaneous structure imager using realtime nonlinear video processing

A method includes placing an imaging device in contact with a sample, irradiating the sample via an illuminator such that radiation scatters off of the structure, and providing the scattered radiation to a detector to generate a digital video signal. A processor then performs various operations including subtracting a sum of a black state value and a user-defined black level clamping value from the digital video signal to create subtracted image data, substituting negative values in the subtracted image data with a reference value to create modified image data, and amplifying the modified image data by a user-defined gain to create contrast enhanced image data.

Krasowski, Michael J.↗
DOE OSTI2021

Methods and devices for preventing computationally explosive calculations in a computer for model parameters distributed on a hierarchy of geometric simplices

A computer-implemented method of preventing computationally explosive calculations. The method includes obtaining, by a processor of the computer, measured data of one of a physical process or a physical object; performing hierarchical numerical modeling of a physical process inclusive of an Earth model containing at least one of (a) infrastructure in the ground and (b) a formation feature in the ground, wherein predicted data is generated; comparing the measured data to the predicted data to calculate an estimated error; analyzing the estimated error via an inversion process to update the at least one of the Earth model and infrastructure model so as to reduce the estimated error and to determine a final composite Earth model of at least one of the infrastructure and the feature; and using the final composite Earth model to characterize at least one of the process and the physical object.

Source record↗
DOE OSTI2021

Implementing a micro-operation cache with compaction

Systems, apparatuses, and methods for compacting multiple groups of micro-operations into individual cache lines of a micro-operation cache are disclosed. A processor includes at least a decode unit and a micro-operation cache. When a new group of micro-operations is decoded and ready to be written to the micro-operation cache, the micro-operation cache determines which set is targeted by the new group of micro-operations. If there is a way in this set that can store the new group without evicting any existing group already stored in the way, then the new group is stored into the way with the existing group(s) of micro-operations. Metadata is then updated to indicate that the new group of micro-operations has been written to the way. Additionally, the micro-operation cache manages eviction and replacement policy at the granularity of micro-operation groups rather than at the granularity of cache lines.

Kotra, Jagadish B.↗
DOE OSTI2021

Passive method to measure strength of turbulence

Disclosed is a method to passively measure and calculate the strength of turbulence via the index of refraction structure constant Cn2 from video imagery gathered by an imaging device, such as a video camera. Processing may occur with any type computing device utilizing a processor executing machine executable code stored on memory. This method significantly simplifies instrumentation requirements, reduces cost, and provides rapid data output. This method combines an angle of arrival methodology, which provides scale factors, with a new spatial/temporal frequency domain method. As part of the development process, video imagery from high speed cameras was collected and analyzed. The data was decimated to video rates such that statistics could be computed and used to confirm that this passive method accurately characterizes the atmospheric turbulence. Cn2 accuracy from this method compared well with scintillometer data through two full orders of magnitude and more capability is expected beyond this verification.

O'Neill, Mary Morabito↗
DOE OSTI2021

Method and apparatus for radiation detection based on time-of-flight within optical fibers

A radiation detection system using time of flight (TOF) information within multiple optical fiber complexes coupled with a scintillating material at intersections of repeatedly crossing over shape. Light detectors are placed at the ends of each fiber to detect scintillation events. A timing processor is collecting light detector signal to compute TOF difference and estimate the location and strength of radioactivity. The system is scalable in one dimension, capable of being shaped or curved, and customizable in terms of special resolution and sensitivity. The system is suitable for long range and coarse radiation detection.

Lee, Seung Jae↗
DOE OSTI2021

Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems

Graphics Processing Units (GPUs) are ubiquitous components used across the range of today’s computing plat- forms, from phones and tablets, through personal computers, to high-end server class platforms. With the increasing importance of graphics and video workloads, recent processors are shipped with GPU devices that are integrated on the same chip. Integrated GPUs share some resources with the CPU and as a result, there is a potential for microarchitectural attacks from the GPU to the CPU or vice versa. We consider the potential for covert channel attacks that arise either from shared microarchitectural components (such as caches) or through shared contention domains (e.g., shared buses). We illustrate these two types of channels by developing two reliable covert channel attacks. The first covert channel uses the shared LLC cache in Intel’s integrated GPU architectures. The second is a contention based channel targeting the ring bus connecting the CPU and GPU to the LLC. This is the first demonstrated microarchitectural attack crossing the component boundary (GPU to CPU or vice versa). Cross-component channels introduce a number of new challenges that we had to overcome since they occur across heterogeneous components that use different computation models and are interconnected using asymmetric memory hierarchies. We also exploit GPU parallelism to increase the bandwidth of the communication, even without relying on a common clock. The LLC based channel achieves a bandwidth of 120 kbps with a low error rate of 2%, while the contention based channel delivers up to 400 kbps with a 0.8% error rate. We also demonstrate a proof- of-concept prime-and-probe side channel attack that probes the full LLC from the GPU.

Cyber secruity, high performance comptuing, Hetero↗