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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 847 records · Page 47
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

The NASA SETI Program - Objectives of the R&D activity

The current activity in NASA's SETI Program is a research and development program jointly carried out by the NASA Ames Research Center and the Jet Propulsion Laboratory. The purpose of this R&D phase is to develop all prerequisites for a well defined microwave observing program. The specific objectives include the development of a prototype search system which will ultimately be capable of processing data rates up to 10 gigabytes/second. Specialized signal detection algorithms and automated search procedures will be developed and tested with the prototype hardware. A series of field tests will be carried out with the NASA Deep Space Network facilities at Goldstone, CA and with the 305-m radio telescope at the Arecibo Ionospheric Observatory in Puerto Rico.

Klein, M. J.↗
NASA NTRS1985

Advances and trends in structures and dynamics; Proceedings of the Symposium, Washington, DC, October 22-25, 1984

Among the topics discussed are developments in structural engineering hardware and software, computation for fracture mechanics, trends in numerical analysis and parallel algorithms, mechanics of materials, advances in finite element methods, composite materials and structures, determinations of random motion and dynamic response, optimization theory, automotive tire modeling methods and contact problems, the damping and control of aircraft structures, and advanced structural applications. Specific topics covered include structural design expert systems, the evaluation of finite element system architectures, systolic arrays for finite element analyses, nonlinear finite element computations, hierarchical boundary elements, adaptive substructuring techniques in elastoplastic finite element analyses, automatic tracking of crack propagation, a theory of rate-dependent plasticity, the torsional stability of nonlinear eccentric structures, a computation method for fluid-structure interaction, the seismic analysis of three-dimensional soil-structure interaction, a stress analysis for a composite sandwich panel, toughness criterion identification for unidirectional composite laminates, the modeling of submerged cable dynamics, and damping synthesis for flexible spacecraft structures.

Noor, A. K.↗
NASA NTRS1993

Bandwidth characteristics of multimedia data traffic on a local area network

Limited spacecraft communication links call for users to investigate the potential use of video compression and multimedia technologies to optimize bandwidth allocations. The objective was to determine the transmission characteristics of multimedia data - motion video, text or bitmap graphics, and files transmitted independently and simultaneously over an ethernet local area network. Commercial desktop video teleconferencing hardware and software and Intel's proprietary Digital Video Interactive (DVI) video compression algorithm were used, and typical task scenarios were selected. The transmission time, packet size, number of packets, and network utilization of the data were recorded. Each data type - compressed motion video, text and/or bitmapped graphics, and a compressed image file - was first transmitted independently and its characteristics recorded. The results showed that an average bandwidth of 7.4 kilobits per second (kbps) was used to transmit graphics; an average bandwidth of 86.8 kbps was used to transmit an 18.9-kilobyte (kB) image file; a bandwidth of 728.9 kbps was used to transmit compressed motion video at 15 frames per second (fps); and a bandwidth of 75.9 kbps was used to transmit compressed motion video at 1.5 fps. Average packet sizes were 933 bytes for graphics, 498.5 bytes for the image file, 345.8 bytes for motion video at 15 fps, and 341.9 bytes for motion video at 1.5 fps. Simultaneous transmission of multimedia data types was also characterized. The multimedia packets used transmission bandwidths of 341.4 kbps and 105.8kbps. Bandwidth utilization varied according to the frame rate (frames per second) setting for the transmission of motion video. Packet size did not vary significantly between the data types. When these characteristics are applied to Space Station Freedom (SSF), the packet sizes fall within the maximum specified by the Consultative Committee for Space Data Systems (CCSDS). The uplink of imagery to SSF may be performed at minimal frame rates and/or within seconds of delay, depending on the user's allocated bandwidth. Further research to identify the acceptable delay interval and its impact on human performance is required. Additional studies in network performance using various video compression algorithms and integrated multimedia techniques are needed to determine the optimal design approach for utilizing SSF's data communications system.

Chuang, Shery L.↗
NASA NTRS1995

Parallel Processing with Digital Signal Processing Hardware and Software

The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

Swenson, Cory V.↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
DOE OSTI2022

Estimating the randomness of quantum circuit ensembles up to 50 qubits

Random quantum circuits have been utilized in the contexts of quantum supremacy demonstrations, variational quantum algorithms for chemistry and machine learning, and blackhole information. The ability of random circuits to approximate any random unitaries has consequences on their complexity, expressibility, and trainability. To study this property of random circuits, we develop numerical protocols for estimating the frame potential, the distance between a given ensemble and the exact randomness. Our tensor-network-based algorithm has polynomial complexity for shallow circuits and is high-performing using CPU and GPU parallelism. We study 1. local and parallel random circuits to verify the linear growth in complexity as stated by the Brown–Susskind conjecture, and; 2. hardware-efficient ansätze to shed light on its expressibility and the barren plateau problem in the context of variational algorithms. Our work shows that large-scale tensor network simulations could provide important hints toward open problems in quantum information science.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

Quantum Computing in Next-Generation Transportation Optimization

We explore how quantum computing (QC) can advance transportation optimization, with a focus on two high-impact areas: traffic signal control and vehicle electrification with grid integration. As transportation systems grow in complexity, classical optimization methods increasingly struggle to deliver scalable and efficient solutions, particularly for real-time, data-rich environments. This work identifies key challenges within these two domains where QC may offer advantages, particularly in handling combinatorial decision spaces and dynamic constraints. We begin by outlining the limitations of classical approaches for traffic signal control optimization and electric vehicle charging coordination, highlighting where computational limitations arise. Previous quantum formulations are presented and new formulations are proposed to demonstrate how emerging quantum algorithms, including quantum annealing and the Quantum Approximation Optimization Algorithm, could be leveraged to reformulate and address these problems. We also evaluate the suitability of current quantum hardware and discuss recent trends that indicate when QC may become a viable tool for transportation applications. While acknowledging the present limitations of QC technologies, this poster emphasizes the importance of preparing quantum-compatible models today. By reviewing and establishing formulations that align with the strengths of quantum algorithms, researchers and practitioners can better position themselves to take advantage of QC advancements as they occur. This work aims to provide a practical, forward-looking perspective on the near-term potential of quantum computing in transportation optimization.

33 ADVANCED PROPULSION SYSTEMS↗
NASA NTRS1991

Guidance, navigation, and control subsystem equipment selection algorithm using expert system methods

Enhanced engineering tools can be obtained through the integration of expert system methodologies and existing design software. The application of these methodologies to the spacecraft design and cost model (SDCM) software provides an improved technique for the selection of hardware for unmanned spacecraft subsystem design. The knowledge engineering system (KES) expert system development tool was used to implement a smarter equipment section algorithm than that which is currently achievable through the use of a standard data base system. The guidance, navigation, and control subsystems of the SDCM software was chosen as the initial subsystem for implementation. The portions of the SDCM code which compute the selection criteria and constraints remain intact, and the expert system equipment selection algorithm is embedded within this existing code. The architecture of this new methodology is described and its implementation is reported. The project background and a brief overview of the expert system is described, and once the details of the design are characterized, an example of its implementation is demonstrated.

Allen, Cheryl L.↗
NASA NTRS1992

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Moore, J. Strother↗
DOE OSTI2026

PowerMappeR: Power-Optimized Mapping of SNNs onto ReRAM Crossbars coupled via Packet-Switched NoCs

Many recent efforts in developing hardware-accelerated spiking neural networks (SNNs) are characterized by deep co-design between algorithms, architectures, and devices. Architectural advances overcome device constraints by coupling together many small resistive-RAM (ReRAM) crossbars via a network-on-chip (NoC) for neuromorphic component operation. Concurrently, improved SNN training methods increase accuracy and structural sparsity in networks despite growing problem sizes. Finally, compilers leverage these attributes to minimize area and inter-crossbar communication while mapping large SNNs to sophisticated architectures. However, for compiler-driven co-design to realize increasingly complex and profitable optimizations, a compile-time view of power consumption is critical. We present PowerMappeR to express and optimize over mapping-, architecture-, and device-specific power consumption information. By modeling the dynamic power of well-established components, we develop an integer linear programming (ILP)-based, encoding-agnostic, parametric power estimation model. Using this model, we demonstrate practical improvements in area and inter-crossbar communication by 0%–9.5% and 1.4%–5.1%, respectively. We also limit hotspot formation during optimization, achieving comparable or better results in targeted metrics with up to 96.4%–97.1% restriction of hotspot magnitude. Finally, we introduce profile-guided formulations to reduce worst-case and expected-case hotspot magnitude by 40.7%–69.5% and 40.6%–56.3%, respectively. Optimizing worst-case hotspot magnitude incidentally improves expected-case magnitude by 10.85%–33.45%. Reciprocally, optimizing expected-case magnitude incidentally improves worst-case magnitude by 4.33%–39.87%. Validation against hardware simulators confirms that PowerMappeR can decrease dynamic power consumption by 12.6%–27.3%.

Pohl, Devin [ORNL] (ORCID:0009000040149027)↗
NASA NTRS1998

Attitude Estimation Signal Processing: A First Report on Possible Algorithms and Their Utility

In this brief effort, time has been of the essence. The data had to be acquired from APL/Lincoln Labs, stored, and sorted out to obtain the pertinent streams. This has been a significant part of this effort and hardware and software problems have been addressed with the appropriate solutions to accomplish this part of the task. Passed this, some basic and important algorithms are utilized to improve the performance of the attitude estimation systems. These algorithms are an essential part of the signal processing for the attitude estimation problem as they are utilized to reduce the amount of the additive/multiplicative noise that in general may or may not change its structure and probability density function, pdf, in time. These algorithms are not currently utilized in the processing of the data, at least, we are not aware of their use in this attitude estimation problem. Some of these algorithms, like the variable thresholding, are new conjectures, but one would expect that someone somewhere must have utilized this kind of scheme before. The variable thresholding idea is a straightforward scheme to use in case of a slowly varying pdf, or statistical moments of the unwanted random process. The algorithms here are kept simple but yet effective for processing the data and removing the unwanted noise. For the most part, these algorithms can be arranged so that their consecutive and orderly execution would complement the preceding algorithm and improve the overall performance of the signal processing chain.

Riasati, Vahid R.↗
DOE OSTI2021

Real time evolution for ultracompact Hamiltonian eigenstates on quantum hardware

In this work we present a detailed analysis of variational quantum phase estimation (VQPE), a method based on real-time evolution for ground and excited state estimation on near-term hardware. We derive the theoretical ground on which the approach stands, and demonstrate that it provides one of the most compact variational expansions to date for solving strongly correlated Hamiltonians. At the center of VQPE lies a set of equations, with a simple geometrical interpretation, which provides conditions for the time evolution grid in order to decouple eigenstates out of the set of time evolved expansion states, and connects the method to the classical filter diagonalization algorithm. Further, we introduce what we call the unitary formulation of VQPE, in which the number of matrix elements that need to be measured scales linearly with the number of expansion states, and we provide an analysis of the effects of noise which substantially improves previous considerations. The unitary formulation allows for a direct comparison to iterative phase estimation. Our results mark VQPE as both a natural and highly efficient quantum algorithm for ground and excited state calculations of general many-body systems. We demonstrate a hardware implementation of VQPE for the transverse field Ising model. Further, we illustrate its power on a paradigmatic example of strong correlation (Cr2 in the SVP basis set), and show that it is possible to reach chemical accuracy with as few as ~50 timesteps.

Klymko, Katherine↗
DOE OSTI2024

Adaptive Mesh Refinement Simulations for Turbulent Reacting Flow

With the increased availability of exascale computing hardware, detailed simulations of realistic devices can be performed at practically relevant time and length scales. Insights into the multiscale driving mechanisms in compressible reacting flow systems with complex geometry, such as combustors, can be used for design optimization and technology improvements. However, to effectively perform these simulations, advanced numerical algorithms must be used to maintain solution accuracy without incurring undue computational costs. PeleC, part of the Pele suite of codes, leverages block-structured adaptive mesh refinement (AMR) through the AMReX library to capture fine-scale flow features in compressible reacting flows. In this talk, we discuss recent improvements to the numerical algorithms, particularly in regard to describing flows at complex boundary structures, and PeleC's performance on exascale computing hardware. We will demonstrate that PeleC is well-suited for modern, extreme-scale, heterogenous compute platforms.

combustion↗
DOE OSTI2024

Enhancing scalability and accuracy of quantum poisson solver

The Poisson equation has many applications across the broad areas of science and engineering. Most quantum algorithms for the Poisson solver presented so far either suffer from lack of accuracy and/or are limited to very small sizes of the problem and thus have no practical usage. In this regard, our previous work showed a proof-of-concept demonstration in advancing quantum Poisson solver algorithm and validated preliminary results for a simple case of 3 x 3 problem. In this work, we delve into comprehensive research details, presenting the results on up to 15 x 15 problems that include step-by-step improvements in Poisson equation solutions, scaling performance, and experimental exploration. In particular, we demonstrate the implementation of eigenvalue amplification by a factor of up to 2 8 , achieving a significant improvement in the accuracy of our quantum Poisson solver and comparing that to the exact solution. Additionally, we present success probability results, highlighting the reliability of our quantum Poisson solver. Moreover, we explore the scaling performance of our algorithm against the circuit depth and width, demonstrating how our approach scales with larger problem sizes and thus further solidifies the practicality of easy adaptation of this algorithm in real-world applications. We also discuss a multilevel strategy for how this algorithm might be further improved to explore much larger problems with greater performance. Finally, through our experiments on the IBM quantum hardware, we conclude that though overall results on the existing NISQ hardware are dominated by the error in the CNOT gates, this work opens a path to realizing a multidimensional Poisson solver on near-term quantum hardware.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Algorithms for Efficient Reproducible Floating Point Summation

We define “reproducibility” as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a “reproducible accumulator” data structure (the “binned number”) and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing n words with a 6-word reproducible accumulator requires approximately 9 n floating point operations (arithmetic, comparison, and absolute value) and approximately 3 n bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 2 29 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs.

Computer Science↗
DOE OSTI2021

Athena: High-Performance Sparse Tensor Contraction Sequence on Heterogeneous Memory

Sparse tensor contraction sequence has been widely employed in many fields, such as chemistry and physics. However, how to efficiently implement the sequence faces multiple challenges, such as redundant computations and memory operations, massive memory consumption, and inefficient utilization of hardware. To address the above challenges, we introduce Athena, a high-performance framework for SpTC sequences. Athena introduces new data structures, leverages emerging Optane-based heterogeneous memory (HM) architecture, and stage parallelism. In particular, Athena introduces shared hash table-represented sparse accumulator to eliminate unnecessary input processing and data migration; Athena uses a novel data-semantic guided dynamic migration solution to make the best use of the Optane-based HM for high performance; Athena also co-runs execution phases with different characteristics to enable high hardware utilization. Evaluating with 12 datasets, we show that Athena brings 327-7362× speedup over the state-of-the-art SpTC algorithm. With the dynamic data placement guided by data semantics, Athena brings performance improvement on Optane-based HM over a state-of-the-art software-based data management solution, a hardware-based data management solution, and PMM-only by 1.58×, 1.82×, and 2.34× respectively.

Liu, Jiawen↗
DOE OSTI2022

All-Electric Nonassociative Learning in Nickel Oxide

Habituation and sensitization represent nonassociative learning mechanisms in both non-neural and neural organisms. They are essential for a range of functions from survival to adaptation in dynamic environments. Design of hardware for neuroinspired computing strives to emulate such features driven by electric bias and can also be incorporated into neural network algorithms. Herein, cellular-like learning in oxygen-deficient NiO x devices is demonstrated. Both habituation learning and sensitization response can be achieved in a single device by simply controlling the magnitude of the electric field. Spontaneous memory relaxations and dynamic redistribution of oxygen vacancies under electric bias enable such learning behavior of NiO x under sequential training. These characteristics in simple device arrays are implemented to learn alphabets as well as demonstrate simulated algorithmic use cases in digit recognition. Transition metal oxides with carefully prepared defect concentrations can be highly sensitive to electronic structure perturbations under moderate electrical stimulus and serve as building blocks for next-generation neuroinspired computing hardware.

36 MATERIALS SCIENCE↗
NASA NTRS1991

Control algorithm implementation for a redundant degree of freedom manipulator

This project's purpose is to develop and implement control algorithms for a kinematically redundant robotic manipulator. The manipulator is being developed concurrently by Odetics Inc., under internal research and development funding. This SBIR contract supports algorithm conception, development, and simulation, as well as software implementation and integration with the manipulator hardware. The Odetics Dexterous Manipulator is a lightweight, high strength, modular manipulator being developed for space and commercial applications. It has seven fully active degrees of freedom, is electrically powered, and is fully operational in 1 G. The manipulator consists of five self-contained modules. These modules join via simple quick-disconnect couplings and self-mating connectors which allow rapid assembly/disassembly for reconfiguration, transport, or servicing. Each joint incorporates a unique drive train design which provides zero backlash operation, is insensitive to wear, and is single fault tolerant to motor or servo amplifier failure. The sensing system is also designed to be single fault tolerant. Although the initial prototype is not space qualified, the design is well-suited to meeting space qualification requirements. The control algorithm design approach is to develop a hierarchical system with well defined access and interfaces at each level. The high level endpoint/configuration control algorithm transforms manipulator endpoint position/orientation commands to joint angle commands, providing task space motion. At the same time, the kinematic redundancy is resolved by controlling the configuration (pose) of the manipulator, using several different optimizing criteria. The center level of the hierarchy servos the joints to their commanded trajectories using both linear feedback and model-based nonlinear control techniques. The lowest control level uses sensed joint torque to close torque servo loops, with the goal of improving the manipulator dynamic behavior. The control algorithms are subjected to a dynamic simulation before implementation.

Cohan, Steve↗