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At least 847 records · Page 47
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony concentration was approximately 4 x 10(exp 19) per cubic centimeter. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per square centimeter, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V (sub DS)) range, with V (sub DS) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Alterovitz, Samuel A.↗
NASA NTRS2004

High Mobility SiGe/Si n-MODFET Structures and Devices on Sapphire Substrates

Si/Ge/Si n-type modulation doped field effect structures and transistors (n-MODFET's) have been fabricated on r-plane sapphire substrates. Mobilities as high as 1380 cm(exp 2)/Vs were measured at room temperature. Excellent carrier confinement was shown by Shubnikov-de Haas measurements. Atomic force microscopy indicated smooth surfaces, with rm's roughness less than 4 nm, similar to the quality of SiGe/Si n-MODFET structures made on Si substrates. Transistors with 2 micron gate lengths and 200 micron gate widths were fabricated and tested.

Mueller, Carl↗
DOE OSTI2020

Gate-Tunable Semiconductor Heterojunctions from 2D/3D van der Waals Interfaces

Van der Waals (vdW) semiconductors are attractive for highly scaled devices and heterogeneous integration since they can be isolated into self-passivated, two-dimensional (2D) layers that enable superior electrostatic control. These attributes have led to numerous demonstrations of field-effect devices ranging from transistors to triodes. By exploiting the controlled, substitutional doping schemes in covalently-bonded, three-dimensional (3D) semiconductors and the passivated surfaces of 2D semiconductors, one can construct devices that can exceed performance metrics of “all-2D” vdW heterojunctions. Here, we demonstrate, 2D/3D semiconductor heterojunctions using MoS2 as the prototypical 2D semiconductor laid upon Si and GaN as the 3D semiconductor layers. By tuning the Fermi levels in MoS2, we demonstrate devices that concurrently exhibit over seven orders of magnitude modulation in rectification ratios and conductance. Our results further suggest that the interface quality does not necessarily affect Fermi-level tuning at the junction opening up possibilities for novel 2D/3D heterojunction device architectures

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2011

High-Tc Superconducting Bolometer Noise Measurement Using Low Noise Transformers - Theory and Optimization

Care must always be taken when performing noise measurements on high-Tc superconducting materials to ensure that the results are not from the measurement system itself. One situation likely to occur is with low noise transformers. One of the least understood devices, it provides voltage gain for low impedance inputs (< 100 ), e.g., YBaCuO and GdBaCuO thin films, with comparatively lower noise levels than other devices for instance field effect and bipolar junction transistors. An essential point made in this paper is that because of the complex relationships between the transformer ports, input impedance variance alters the transformer s transfer function in particular, the low frequency cutoff shift. The transfer of external and intrinsic transformer noise to the output along with optimization and precautions are treated; all the while, we will cohesively connect the transfer function shift, the load impedance, and the actual noise at the transformer output.

Aslam, Shahid↗
NASA NTRS2004

EHW Approach to Temperature Compensation of Electronics

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

Stoica, Adrian↗
NASA NTRS2005

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

evolvable hardware↗
DOE OSTI2023

Determining the Electronic Structure and Thermoelectric Properties of MoS 2 /MoSe 2 Type‐I Heterojunction by DFT and the Landauer Approach

Abstract The electronic structure and thermoelectric properties of MoX 2 (X = S, Se) Van der Waals heterojunctions are reported, with the intention of motivating the design of electronic devices using such materials. Calculations indicate the proposed heterojunctions are thermodynamically stable and present a band gap reduction from 1.8 eV to 0.8 eV. The latter effect is highly related to interactions between metallic d‐character orbitals and chalcogen p‐character orbitals. The theoretical approach allows to predict a transition from semiconducting to semi‐metallic behavior. The band alignment indicates a type‐I heterojunction and band offsets of 0.2 eV. Transport properties show clear n‐type nature and a high Seebeck coefficient at 300 K, along with conductivity values (σ/τ) in the order of 10 20 . Lastly, using the Landauer approach and ballistic transport, the proposed heterojunctions can be modeled as a channel material for a typical one‐gate transistor configuration predicting subthreshold values of ≈60 mV dec −1 and field–effect mobilities of ≈160 cm −2 V −1 s −1 .

López‐Galán, Oscar A.↗
NASA NTRS1972

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗
NASA NTRS1994

Nonvolatile random access memory

A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

Wu, Jiin-Chuan↗
DOE OSTI2020

Experimental and theoretical evidence for hydrogen doping in polymer solution-processed indium gallium oxide

The field-effect electron mobility of aqueous solution-processed indium gallium oxide (IGO) thin-film transistors (TFTs) is significantly enhanced by polyvinyl alcohol (PVA) addition to the precursor solution, a >70-fold increase to 7.9 cm 2 /Vs. To understand the origin of this remarkable phenomenon, microstructure, electronic structure, and charge transport of IGO:PVA film are investigated by a battery of experimental and theoretical techniques, including In K-edge and Ga K-edge extended X-ray absorption fine structure (EXAFS); resonant soft X-ray scattering (R-SoXS); ultraviolet photoelectron spectroscopy (UPS); Fourier transform-infrared (FT-IR) spectroscopy; time-of-flight secondary-ion mass spectrometry (ToF-SIMS); composition-/processing-dependent TFT properties; high-resolution solid-state 1 H, 71 Ga, and 115 In NMR spectroscopy; and discrete Fourier transform (DFT) analysis with ab initio molecular dynamics (MD) liquid-quench simulations. The 71 Ga{ 1 H} rotational-echo double-resonance (REDOR) NMR and other data indicate that PVA achieves optimal H doping with a Ga···H distance of ~3.4 Å and conversion from six- to four-coordinate Ga, which together suppress deep trap defect localization. This reduces metal-oxide polyhedral distortion, thereby increasing the electron mobility. Finally, hydroxyl polymer doping thus offers a pathway for efficient H doping in green solvent-processed metal oxide films and the promise of high-performance, ultra-stable metal oxide semiconductor electronics with simple binary compositions.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1991

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

Wu, Jiin C.↗
DOE OSTI2023

Record high room temperature resistance switching in ferroelectric-gated Mott transistors unlocked by interfacial charge engineering

Abstract The superior size and power scaling potential of ferroelectric-gated Mott transistors makes them promising building blocks for developing energy-efficient memory and logic applications in the post-Moore’s Law era. The close to metallic carrier density in the Mott channel, however, imposes the bottleneck for achieving substantial field effect modulation via a solid-state gate. Previous studies have focused on optimizing the thickness, charge mobility, and carrier density of single-layer correlated channels, which have only led to moderate resistance switching at room temperature. Here, we report a record high nonvolatile resistance switching ratio of 38,440% at 300 K in a prototype Mott transistor consisting of a ferroelectric PbZr 0.2 Ti 0.8 O 3 gate and an R NiO 3 ( R : rare earth)/La 0.67 Sr 0.33 MnO 3 composite channel. The ultrathin La 0.67 Sr 0.33 MnO 3 buffer layer not only tailors the carrier density profile in R NiO 3 through interfacial charge transfer, as corroborated by first-principles calculations, but also provides an extended screening layer that reduces the depolarization effect in the ferroelectric gate. Our study points to an effective material strategy for the functional design of complex oxide heterointerfaces that harnesses the competing roles of charge in field effect screening and ferroelectric depolarization effects.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2002

Rapid evolution of analog circuits configured on a field programmable transistor array

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

SABLES analog circuits field programmable transist↗
DOE OSTI2026

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗
DOE OSTI2023

Heavy ion irradiation induced failure of gallium nitride high electron mobility transistors: effects of in-situ biasing

Abstract While radiation is known to degrade AlGaN/GaN high-electron-mobility transistors (HEMTs), the question remains on the extent of damage governed by the presence of an electrical field in the device. In this study, we induced displacement damage in HEMTs in both ON and OFF states by irradiating with 2.8 MeV Au 4+ ion to fluence levels ranging from 1.72 × 10 10 to 3.745 × 10 13 ions cm −2 , or 0.001–2 displacement per atom (dpa). Electrical measurement is done in situ , and high-resolution transmission electron microscopy (HRTEM), energy dispersive x-ray (EDX), geometrical phase analysis (GPA), and micro-Raman are performed on the highest fluence of Au 4+ irradiated devices. The selected heavy ion irradiation causes cascade damage in the passivation, AlGaN, and GaN layers and at all associated interfaces. After just 0.1 dpa, the current density in the ON-mode device deteriorates by two orders of magnitude, whereas the OFF-mode device totally ceases to operate. Moreover, six orders of magnitude increase in leakage current and loss of gate control over the 2-dimensional electron gas channel are observed. GPA and Raman analysis reveal strain relaxation after a 2 dpa damage level in devices. Significant defects and intermixing of atoms near AlGaN/GaN interfaces and GaN layer are found from HRTEM and EDX analyses, which can substantially alter device characteristics and result in complete failure.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1979

Heavily doped transparent-emitter regions in junction solar cells, diodes, and transistors

The paper presents an analytical treatment of transparent-emitter devices, particularly solar cells, that is more complete than previously available treatments. The proposed approach includes the effects of bandgap narrowing, Fermi-Dirac statistics, built-in field due to impurity profile, and a finite surface recombination velocity at the emitter surface. It is demonstrated that the transparent-emitter model can predict experimental values of Voc observed on n(plus)-p thin diffused junction silicon solar cells made on low-resistivity (0.1 ohm-cm) substrates. A test is included for the self-consistent validity of the transparent-emitter model. This test compares the calculated transit time of minority carriers across the emitter with the Auger-impact minority-carrier lifetime within the emitter region.

Shibib, M. A.↗
DOE OSTI2023

Wafer-scale growth of two-dimensional, phase-pure InSe

Two-dimensional (2D) indium monoselenide (InSe) has attracted significant attention as an ultrathin III–VI semiconductor with a combination of favorable attributes that are comparable to those of III–V semiconductors and van der Waals 2D transition-metal dichalcogenides. Nevertheless, there has been no demonstration of large-area synthesis of 2D InSe due to the complexity of the binary In-Se system and the difficulties in promoting lateral growth. Here, we report the polymorph-selective synthesis of epitaxial 2D InSe by metal-organic chemical vapor deposition (MOCVD) over 2-in wafers. We achieve polymorph-selective epitaxial growth of InSe on c-plane sapphire via flow modulation to control the Se/In ratio. The layer-by-layer growth allows thickness control with tunable optical properties comparable to those of bulk crystals. We also demonstrate gate-tunable electrical transport with a field-effect mobility comparable to that of single-crystalline flakes. Importantly, these results indicate that InSe grown by MOCVD could be an effective channel material for back-end-of-line integration in logic transistors.

2D materials↗
DOE OSTI2020

Negative capacitance regime in ferroelectrics demystified from nonequilibrium molecular dynamics

Negative capacitance regime in ferroelectrics is associated with the negative slope in the dependence of the polarization on electric field and is prohibited by the laws of equilibrium thermodynamics. Very recently, it developed into a controversial but very productive area with a promise for next generation low-power transistors. At least, in part, the controversies arise from the lack of direct experimental insight into the mechanism for such phenomena. Although the experimental insight is, indeed, challenging at present, we probe the effect in ferroelectric PbTiO 3 bulk and a thin film with realistic first-principles-based nonequilibrium molecular dynamics simulations which model most closely experimental conditions. Here, the following insights emerge from the simulations: (i) the ferroelectric never enters the thermodynamically forbidden region even under extreme rates of electric-field application; (ii) the negative slope naturally arises when the compensating charge is either scarce or slowed down by the external circuitry; (iii) the negative slope is well controlled by the interplay between the applied step pulse field and the amount of the screening charge. The latter can be used to design the negative capacitance regime.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗