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At least 847 records · Page 47
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Mass Spectra Deconvolution of Gaseous Mixtures Containing Volatile Organic Compounds

The Spacecraft Atmosphere Monitor (S.A.M.) analyzes all gaseous pollutants in the 1-150Th mass-to-charge range based on their positive-ion mass spectra. Of particular interest is the Trace Gas Analysis (TGA) mode of operation in which S.A.M detects minute amounts of volatile organic compounds (VOC). Pollutant component of the ambient air is sampled on demand in twenty full mass spectra per second. All spectra is accumulated in two-second intervals by an on-board Field Programmable Gate Arrays (FPGA) unit. Mass spectra represents the number of detected fragment ions in a given mass-to-charge ratio channel. Electron impact ionization of neutral molecules results in creation of numerous fragment ions and most of organic compounds will contribute several identical fragments. Despite the presence of these molecular isobars, we developed the deconvolution algorithm capable of identifying target species based on their characteristic fragmentation patterns. We investigate the efficiency of deconvolution algorithm as a function of mass resolution with which mass spectrum is acquired. Higher the mass resolution, better the chances are to distinguish between stereoisomers using their fragmentation propensities, but also results in higher data volumes to be processed by a set of small footprint software stacks hosted by an on-board computer. Finding the balance between deconvolution accuracy and generated data volume under time constrains and limited computing resources is the main topic of this study.

Darrach, M.↗
NASA NTRS2018

High-Rate Ka-Band Modulator for the NISAR Mission

In order to meet ever-increasing data return requirements, more satellites are using the near-Earth Ka-band (25.5 – 27.0 GHz) to achieve higher downlink rates. The paper discusses the Universal Space Transponder - Ka-band Modulator (UST-KaM) developed at the NASA Jet Propulsion Laboratory for the NASA-ISRO SAR (NISAR) mission, which is capable of transmitting up to 1.74 Gbps with 7/8 LDPC encoding. The UST-KaM utilizes OQPSK with both baseband and RF filtering to contain the 1 Gsps transmission spectrum within the 1.5 GHz Ka-band, even with the use of an external, saturated amplifier. Due to the high data rates involved, several technical hurdles were overcome in both the digital and RF designs. The UST-KaM is a software defined radio with two digital circuit board assemblies: a low speed housekeeper board for commanding and telemetry, and a high-rate signal processing board known as the Signal Processing Module (SPM). The SPM receives data from the spacecraft via a SERDES interface at up to 2 Gbps, processes and encodes the data using a Xilinx Virtex-5 FPGA, and produces 1 Gsps OQPSK I and Q waveforms via synchronized, multiplexed DACs. The RF Electronics in the UST-KaM employ a heterodyne architecture in which the I/Q digital waveforms are filtered and then up-converted using a sub-harmonic IQ mixer. The LO of the converter, which is included in the exciter assembly, is at 13.125GHz, and the RF output is a 26.25GHz carrier which is modulated with the OQPSK waveforms. The output of the mixer is then filtered using low loss quartz thinfilm edge coupled Chebyshev filters and amplified through a series of low gain Ka-Band amplifiers. The exciter assembly also has a 2GHz, low-phase-noise, PLL synthesizer to supply the clock to the DACs for the high rate digital waveforms.

Spurgers, Carl↗
NASA NTRS2018

Context Cameras for the Orbiting Carbon Observatory 3 (OCO-3) Instrument

We have developed an adaptable camera platform that takes advantage of screened and qualified commercial off the shelf (COTS) components (CMOS sensor, rad-tolerant microcircuits, lenses) to significantly shorten development time of space-borne visible imaging systems while reducing the overall cost and risk of the development. This modular camera platform is implemented as a suite of two visible-light cameras for the Orbiting Carbon Observatory 3 (OCO-3) instrument at NASA’s Jet Propulsion Laboratory (JPL). The Internal Context Camera (ICC) and External Context Camera (ECC) provide contextual engineering imaging support for the calibration of the OCO-3 instrument, intended to significantly reduce the duration of the mission’s calibration campaign. The OCO-3 mission has taken advantage of the design and qualification work performed by JPL’s Mars 2020 Enhanced Engineering Camera (EECam) team in reusing the qualified COTS CMOS imaging sensor, proven electronic designs, and scalable field-programmable gate array (FPGA) firmware to meet OCO-3’s mission requirements and resource availability. We will be presenting the steps taken by JPL to design, build, and test the Context Cameras for the OCO-3 mission. We will highlight the design deviations from the Mars2020 EECams and discuss the methodology of tailoring the EECam design for the OCO-3 requirements. Camera imaging capabilities, including focal plane and optical performance, will be presented, as well as a summary of the calibration and environmental test results. Finally, we will discuss the potential for future applications for the Context Cameras.

Moore, Douglas↗
NASA NTRS2018

A Novel 3D DRAM Memory Cube Architecture for Space Applications

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.

Yang-Scharlotta, Jean↗
NASA NTRS2018

High Performance Space Computing with System-on-Chip Instrument Avionics for Space-based Next Generation Imaging Spectrometers (NGIS).

The emergent technology of system-on-chip (SoC) devices promises lighter, smaller, cheaper, and more capable and reliable space electronic systems that could help to unveil some of the most treasured secrets in our universe. This technology is an improvement over the technology that is currently used in space applications, which lags behind stateof-the-art commercial-off-the-shelf (COTS) equipment by several generations. SoC technology integrates all computational power required by next-generation space exploration science instruments onto a single chip. This presentation will describe a Xilinx Zynq-based data acquisition, cloud-screening and compression computing system that has been developed at the Jet Propulsion Laboratory (JPL) for JPL’s Next Generation Imaging Spectrometers (NGIS). The Xilinx Zynq-based Alpha Data hardware assembly fits into a 120mm by 190m by 40mm assembly and uses 9 watts at peak performance. The computing element is a Xilinx Zynq Z7045Q which includes a Kintex-7 FPGA (equivalent to 3 RAD Virtex5 FPGAs in terms of logic cell resources) and dual-core ARM Cortex-A9 Processors (equivalent to 10 RAD750 Power PCs in term of processing capability).

Smith, Adam↗
NASA NTRS2018

High Performance Space Computing with System-on-Chip Instrument Avionics for Space-based Next Generation Imaging Spectrometers (NGIS).

The emergent technology of system-on-chip (SoC) devices promises lighter, smaller, cheaper, and more capable and reliable space electronic systems that could help to unveil some of the most treasured secrets in our universe. This technology is an improvement over the technology that is currently used in space applications, which lags behind state-of-the-art commercial-off-the-shelf (COTS) equipment by several generations. SoC technology integrates all computational power required by next-generation space exploration science instruments onto a single chip. This presentation will describe a Xilinx Zynq-based data acquisition, cloud-screening and compression computing system that has been developed at the Jet Propulsion Laboratory (JPL) for JPL’s Next Generation Imaging Spectrometers (NGIS). The Xilinx Zynq-based Alpha Data hardware assembly fits into a 120mm by 190m by 40mm assembly and uses 9 watts at peak performance. The computing element is a Xilinx Zynq Z7045Q which includes a Kintex-7 FPGA (equivalent to 3 RAD Virtex5 FPGAs in terms of logic cell resources) and dual-core ARM Cortex-A9 Processors (equivalent to 10 RAD750 Power PCs in term of processing capability).

Dolinar, Sam↗
NASA NTRS2019

Demonstration of stereo vision for deorbit descent and landing

This paper describes results from a recent helicopter field test of a binocular stereo vision system for deorbit descent and landing applications. The system consisted of two 18.6˚ field of view cameras mounted 1.7m apart. Post processing of the images showed ranging accuracy better than 1% up to 500m and 17 cm/s velocimetry accuracy at 37m. For a flight system these images could be input into an FPGA-based processor which processes dense stereo and visual odometry in less than 1 second to achieve the stereo ranging frame rates required for soft landing. When coupled with vision based Terrain Relative Navigation this stereo system enables landing accuracies on the order of 10m.

Johnson, Andrew E.↗
NASA NTRS2019

High performance space computing with system-on-chip instrument avionics for space-based Next Generation Imaging Spectrometers (NGIS)

The emergent technology of system-on-chip (SoC) devices promises lighter, smaller, cheaper, and more capable and reliable space electronic systems that could help to unveil some of the most treasured secrets in our universe. This technology is an improvement over the technology that is currently used in space applications, which lags behind state-of-the-art commercial-off-the-shelf (COTS) equipment by several generations. SoC technology integrates all computational power required by next-generation space exploration science instruments onto a single chip. This presentation will describe a Xilinx Zynq-based data acquisition, cloud-screening and compression computing system that has been developed at the Jet Propulsion Laboratory (JPL) for JPL’s Next Generation Imaging Spectrometers (NGIS). The Xilinx Zynq-based Alpha Data hardware assembly fits into a 120mm by 190m by 40mm assembly and uses 9 watts at peak performance. The computing element is a Xilinx Zynq Z7045Q which includes a Kintex-7 FPGA (equivalent to 3 RAD Virtex5 FPGAs in terms of logic cell resources) and dual-core ARM Cortex-A9 Processors (equivalent to 10 RAD750 Power PCs in term of processing capability).

Dolinar, Sam↗
NASA NTRS2021

The Implementation of a Motor Simulator for the Development of the Europa Lander Motor Controller

JPL is developing a motor controller capable of controlling the motors required for landed missions on icy worlds such as Europa and Enceladus. To support this effort, JPL, together with Tech180, is developing a motor simulator capable of simulating various types of motors required for these missions and their operation in the ambient environment. This system is being designed to support three 3-phase brushless DC motors with the ability to expanded to 24 motors. The simulator is able to simulate motors with current draw up to 10 amps, and sensors that range from resolvers, hall sensors, and encoders. The motor simulator design utilizes NI components and LabVIEW software, along with high-speed FPGA hardware. This paper will present an overview of our motor controller, the requirements for the motor simulator, and details of its design along with the test results to date.

Walker, Roy↗
NASA NTRSDate not supplied

Runtime Monitoring with R2U2 for Aircraft Systems with Neural Networks

R2U2 (Realizable, Responsive, Unobtrusive Unit) is a hardware-supported tool and framework for real-time system monitoring and software health management of cyber-physical systems. During system operation, R2U2 continuously monitors properties about safety, performance, and security of the vehicle and its vital components and can perform diagnostic reasoning. Efficient observers for past-time and future-time Metric Temporal Logic, fast reasoners for Bayesian Networks, and model-based prognostics algorithms are key components of R2U2 and designed for minimal computational footprint. R2U2 has been implemented in software supporting ROS, NASA's cFS/cFE, and Simulink and as an FPGA configuration. The synergistic combination of monitors and observers in R2U2 makes it possible to design powerful models for system runtime monitoring, diagnostics, software health management, prognostics, and security monitoring. In this presentation, I will give a detailed overview of the R2U2 architecture and its features and will discuss the application of R2U2 for safety-monitoring of a neural-network based autonomous centerline tracking system (ACT) for autonomous aircraft.

Runtime Monitoring↗
NASA NTRS2021

A High Dynamic-Range Photon-Counting Receiver for Deep Space Optical Communication

The Deep Space Optical Communication (DSOC) project will demonstrate free-space optical communication at almost 3 AU, or 3 orders of magnitude further than any previous attempt. DSOC will utilize the 5m Palomar Hale Telescope to receive the downlink signal, which will couple the downlink light onto an optical table and into a superconducting nanowire single photon detector (SNSPD). The output of the SNSPD is digitized by the Ground Laser Receiver Signal Processing Assembly (GSPA) using a high throughput streaming time to digital converter (TDC). The GSPA is a scalable FPGA-based receiver which demodulates and decodes the DSOC downlink signal through novel signal processing algorithms implemented on Xilinx UltraScale+ FPGAs, as well as Python-based software monitor and control routines. Exploiting the unique TDC-based architecture, the GSPA supports over four orders of magnitude of downlink data rates across multiple orders of magnitude of signal and background powers. In this paper we present an overview of the hardware, firmware and software architectures to implement this system, as well as performance analysis for links ranging from near-Earth to 2.8 AU.

Srinivasan, Meera↗
NASA NTRS2021

NASA-ISRO SAR (NISAR) Mission Status

The National Aeronautics and Space Administration (NASA) in the United States and the Indian Space Research Organisation (ISRO) are developing the NASA-ISRO Synthetic Aperture Radar (NISAR) mission, now planned for launch toward the end of 2022. The mission will exploit synthetic aperture radar to map Earth’s surface every 12 days, persistently on ascending and descending portions of the orbit, over all land and ice-covered surfaces. The mission’s primary objectives will be to study Earth land and ice deformation, and ecosystems, in areas of common interest to the US and Indian science communities. This single observatory solution with an L-band (24 cm wavelength) and S-band (10 cm wavelength) radar has a swath of over 240 km at fine resolution, using full polarimetry where needed. To achieve these unprecedented capabilities, both radars use a reflector-feed system, whereby the feed aperture elements are individually sampled to allow a scan-on-receive (“SweepSAR”) capability at both L-band and S-band. The L-band and S-band electronics and feed apertures, provided by NASA and ISRO respectively, share a common 12-m diameter deployable reflector/boom system, provided by NASA. These two radars, which can operate simultaneously, even with FPGA-based on-board digital beamforming and filtering to reduce data rates, produce prodigious amounts of data. Given the high data rates and ambitious coverage requirements, new technologies for high-rate Ka-band downlink complement these first-of-a-kind radar systems.

Kumar, Raj↗
NASA NTRSDate not supplied

Navigation Doppler Lidar Signal Processing Architecture and Algorithms

A coherent Doppler lidar has been developed to address the need for a high-performance, compact, and cost-effective velocity and altitude sensor onboard landing vehicles. One of the core subsystems within NDL is its signal processing architecture. The primary function of this subsystem is to digitize the analog output of the homodyned signal received from the photo-diode associated with each telescope, process this signal in the frequency domain, and then turn this information into velocity and range measurements. A secondary function of this subsystem is to setup and control the internal components within NDL and to enable the instrument to interface with external systems by receiving commands, sending telemetry, and synchronizing its measurements with external clocks and pulses. This paper will give an overview of the signal processing architecture within NDL. This will include a discussion on its fundamental processing components and the core signal processing algorithms. Command, telemetry and internal component controls will also be discussed as will how the signal processing architecture has also evolved over the years of development. We will discuss provisions for robust operation including Triple-Mode Redundancy (TMR) within NDL’s Field Programmable Gate Array (FPGA) and storage elements, a fault-tolerant boot process, and Error Detection and Correction (EDAC) on the Static Random-Access Memories (SRAMs). Finally, we conclude this paper with how this architecture could continue to evolve.

Doppler Lidar↗
NASA NTRSDate not supplied

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

heterogeneous processing system↗
NASA NTRS2022

Cold Survivable Electronics Motor Control Law Implementation

For the last seven years JPL has been developing motor control electronics for use on future missions to extreme environments such as Europa and Mars. The packaging technology developed will allow the electronics to survive the extremes seen on the surface. This packaging technology allows us to package everything to control a number of motors on a single card including the closed loop control. In order to improve the performance of the motor control we have developed FPGA code to close the position, velocity and current control loops of the motor controller. This code allowed for a significant improvement in loop rate allowing the control of the motors to be more accurate. This allows for more accurate control of descent engines, more precise control of robotic arm motors. In this paper we will present the design of the control algorithm, the performance of the sensors and the test results of the resulting system.

Cheng, Ben↗
NASA NTRS2022

Benchmarking and Testing of Qualcomm Snapdragon System-on-Chip for JPL Space Applications and Missions

As some space missions become more challenging due to new environments, greater distances, or more limited size, weight, and power (SWaP) constraints, spacecraft avionics must adapt to allow the spacecraft to be more autonomous and agile---eliminating the Spacecraft-Earth-Spacecraft feedback loop whenever possible. Prime examples of such missions include Aerobots (such as Ingenuity with extremely low SWaP constraints and demanding signal/image processing during flight) and landers in possibly hostile environments (such as a Europa lander mission, with limited communication capacity, high latency, and constrained power budget). To address these challenges, JPL worked with Qualcomm to demonstrate the use of their Snapdragon 801 system-on-chip (SoC) onboard the Ingenuity Helicopter on Mars. The Qualcomm Snapdragon SoC contains various subsystems, including an ARM cluster, a Graphics processing unit, a Digital Signal Processing subsystem, a Neural Processing Engine, Image Signal Processing subsystem, among others. Since the success of Ingenuity, JPL is continuing to work with Qualcomm to address other applications of the Snapdragon SoC technology. This includes the deployment of two 855 Snapdragon development boards onboard the International Space Station (ISS) for successful in-situ benchmarking of applications in space (beyond those tested on Ingenuity). In this paper, we will examine the performance of various applications that have been identified to benefit from greater onboard computational capability. These applications include (among others): machine vision algorithms that are expected to be critical in autonomous entry-descent-and-landing scenarios and real-time Aerobot flight navigation; Hyperspectral compression algorithms; Synthetic Aperture Radar Processing along with various instrument processing algorithms. We discuss how the infusion of Qualcomm's Snapdragon SoC is capable of enabling missions that may not have been able to achieve their goals with traditional flight computing. In addition, we also show that for some algorithms, the software implementation on the Snapdragon SoC outperforms traditional FPGA implementations.

Cretu, Vlad↗
NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) developed and previously characterized a photon-counting optical ground receiver system. The receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization High Photon Efficiency (HPE) Standard. The standard will be used on the Optical Artemis-2 Orion (O2O) communications demonstration and the Deep Space Optical Communication (DSOC) project aboard the Psyche spacecraft. The receiver system consists of a fiber interconnect, up to sixteen superconducting nanowire single-photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Previously, the receiver system architecture was described and test results without emulated link effects were presented. SNSPD device properties, which impact detection jitter and time delay, can limit the receiver dynamic range, especially when operating with varying flux rates (>10 dB) between detectors. Codeword error-rate curves with and without simulated clock drifts attributed to Doppler shift and space transmitter clock differences are presented. Results with ±66 ppm clock differences show minimal performance impact (<0.2 dB). Test results show that the receiver dynamic range (>28 dB) is limited by changing SNSPD detection delays at high photon flux rates.

optical communications↗
NASA NTRS2023

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

David K. Rutishauser↗