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At least 847 records · Page 47

Low phase noise digital frequency divider

A low phase noise frequency divider composed of a grating arrangement is disclosed. The grating arrangement supplies selected portions of an input reference signal to be divided to a tuned circuit without any phase noise due to the grating action. The arrangement which in one embodiment consists of an FET is connected to the tuned circuit input to short out the input except when the input reference signal amplitude crosses ground level in a positive direction and a gate enabling signal is present at the gate electrode of the FET. The gate enabling signal alone does not decouple the tuned circuit input from ground, therefore phase noise, due to the leading and trailing edges of each gate-enabling signal, is substantially eliminated.

Lutes, G. F., Jr.↗

Low-Loss, High-Isolation Microwave Microelectromechanical Systems (MEMS) Switches Being Developed

Switches, electrical components that either permit or prevent the flow of electricity, are the most important and widely used electrical devices in integrated circuits. In microwave systems, switches are required for switching between the transmitter and receiver; in communication systems, they are needed for phase shifters in phased-array antennas, for radar and communication systems, and for the new class of digital or software definable radios. Ideally, switches would be lossless devices that did not depend on the electrical signal's frequency or power, and they would not consume electrical power to change from OFF to ON or to maintain one of these two states. Reality is quite different, especially at microwave frequencies. Typical switches in microwave integrated circuits are pin diodes or gallium arsenide (GaAs) field-effect transistors that are nonlinear, with characteristics that depend on the power of the signal. In addition, they are frequency-dependent, lossy, and require electrical power to maintain a certain state. A new type of component has been developed that overcomes most of these technical difficulties. Microelectromechanical (MEMS) switches rely on mechanical movement as a response to an applied electrical force to either transmit or reflect electrical signal power. The NASA Glenn Research Center has been actively developing MEMS for microwave applications for over the last 5 years. Complete fabrication procedures have been developed so that the moving parts of the switch can be released with near 100-percent yield. Moreover, the switches fabricated at Glenn have demonstrated state-of-the-art performance. A typical MEMS switch is shown. The switch extends over the signal and ground lines of a finite ground coplanar waveguide, a commonly used microwave transmission line. In the state shown, the switch is in the UP state and all the microwave power traveling along the transmission line proceeds unimpeded. When a potential difference is applied between the cantilever and the transmission line, the cantilever is pulled downward until it connects the signal line to the ground planes, creating a short circuit. In this state, all the microwave power is reflected. The graph shows the measured performance of the switch, which has less than 0.1 dB of insertion loss and greater than 30dB of isolation. These switches consume negligible electrical power and are extremely linear. Additional research is required to address reliability and to increase the switching speed.

Ponchak, George E.↗

Command Interface ASIC - Analog Interface ASIC Chip Set

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

Ruiz, Baldes↗

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗

Detailed modeling of the video signal and optimal readout of charge-coupled devices

This paper provides a practical design methodology to calculate an optimal filter for noise reduction in the readout of charge-coupled devices (CCDs) taking into account the charge transfer and feedthroughs due to capacitive coupling in the CCD. A detailed analysis of the dynamics of the video signal and charge transfer is presented, including the circuital modeling of the output stage of the CCD and the dynamics of the electronics in the video chain before the analog-to-digital (AD) converter. This model is used to compute an optimal filter that minimizes the variance of the pixel noise and uses the samples of the charge transfer, before the charge is fully settled. This is necessary to enhance the performance of previous results that also use optimal filters but do not use the transition samples, while also reducing the pixel readout time, resulting in faster readouts. As a proof of concept for the optimal filter, we present in this paper novel experimental results using a Skipper CCD, which has a floating sense node that allows to measure the charge packet an arbitrary number of times. However, this technique can be applied to any CCD that has a readout system that digitally samples the video signal.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

HunStat – a simple and low-cost potentiostat for analytical and educational purposes

We have developed a truly low-cost (15 USD), simple do-it-yourself (DIY) potentiostat with compact dimensions. The output potential range of this device is between ±1.65 V. The developed instrument takes advantage of a Seeeduino XIAO microcontroller equipped with 10 bit digital-to-analog (D/A) and 12 bit analog-to-digital (A/D) converters and supports various voltammetry techniques, including cyclic voltammetry (CV), differential pulse voltammetry (DPV), and chronoamperometry (CA). Interested users are provided with circuit diagrams, bill of materials, and design files. Additionally, software components are also provided free of charge, including an Arduino sketch and control software. The software enables easy manipulation of electrochemical parameters and visualization of results. The presented design introduces a simple and low-cost DIY potentiostat recommended for both analytical and educational purposes.

47 OTHER INSTRUMENTATION↗

Speech coding at 4800 bps for mobile satellite communications

A speech compression project has recently been completed to develop a speech coding algorithm suitable for operation in a mobile satellite environment aimed at providing telephone quality natural speech at 4.8 kbps. The work has resulted in two alternative techniques which achieve reasonably good communications quality at 4.8 kbps while tolerating vehicle noise and rather severe channel impairments. The algorithms are embodied in a compact self-contained prototype consisting of two AT and T 32-bit floating-point DSP32 digital signal processors (DSP). A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. On a wirewrapped card, the prototype's circuit footprint amounts to only 200 sq cm, and consumes about 9 watts of power.

Gersho, Allen↗

Implementing neural nets with programmable logic

Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.

Vidal, Jacques J.↗

Circuit For Current-vs.-Voltage Tests Of Semiconductors

Circuit designed for measurement of dc current-versus-voltage characteristics of semiconductor devices. Operates in conjunction with x-y pen plotter or digital storage oscilloscope, which records data. Includes large feedback resistors to prevent high currents damaging device under test. Principal virtues: low cost, simplicity, and compactness. Also used to evaluate diodes and transistors.

Huston, Steven W.↗

Resolving Phase Ambiguities In OQPSK

Improved design for modulator and demodulator in offset-quaternary-phase-key-shifting (OQPSK) communication system enables receiver to resolve ambiguity in estimated phase of received signal. Features include unique-code-word modulation and detection and digital implementation of Costas loop in carrier-recovery subsystem. Enchances performance of carrier-recovery subsystem, reduces complexity of receiver by removing redundant circuits from previous design, and eliminates dependence of timing in receiver upon parallel-to-serial-conversion clock.

Nguyen, Tien M.↗

Approaches and Analysis for On-Focal-Plane Analog-to-Digital Conversion

This paper presents approaches for on-focal-plane analog-to-digital conversion (ADC). Common approaches and architectures for ADC and their utility for on-focal-plane integration are discussed. Candidate approaches are analyzed with respect to required amplifier gain, bandwidth, capacitance matching, noise and offsets as a function of ADC resolution. A column-parallel ADC architecture appears to be an effective compromise of chip area, power, circuit speed and ADC resolution. The discussion is valid for both infrared focal-plane arrays (FPAs) and visible image sensors.

analog-to-digital↗

Spread Spectrum Time Domain Reflectometry (SSTDR) Digital Twin Simulation of Photovoltaic Systems for Fault Detection and Location

Utilizing spread spectrum time domain reflectometry (SSTDR) to detect, locate, and characterize faults in photovoltaic (PV) systems is examined in this paper. We present a method to obtain the model parameters that are needed to produce digital twin SSTDR responses for PV systems. The digital twin SSTDR responses could be used to predict faults within the PV systems. Here, the model parameters are the reflection and transmission coefficients at each impedance discontinuity in the PV system along with the propagation coefficients across each PV cable segment. We obtain model parameter by applying inverse modeling techniques to experimental SSTDR data associated with PV systems. Our model parameters can be used in any digital twin simulation method for modeling reflectometry in frequency-dependent and complex loads. For validation, we used the model parameters in a graph network simulation engine and adapted it to be used for SSTDR digital twin simulations in PV systems. We produced simulations for 0 to 10 PV modules connected in series. We also simulated SSTDR responses for open circuit disconnections in a PV setup containing 10 PV modules in series. Results show that all but one simulated disconnect locations match experimental disconnection locations of the same setup with an error of less than 5%.

14 SOLAR ENERGY↗

Digital communication system

A digital communication system is reported for parallel operation of 16 or more transceiver units with the use of only four interconnecting wires. A remote synchronization circuit produces unit address control words sequentially in data frames of 16 words. Means are provided in each transceiver unit to decode calling signals and to transmit calling and data signals. The transceivers communicate with each other over one data line. The synchronization unit communicates the address control information to the transceiver units over an address line and further provides the timing information over a clock line. A reference voltage level or ground line completes the interconnecting four wire hookup.

Monford, L. G., Jr.↗

Digital time slot display for Omega receiver

Methods of decoding a digital word to display alpha-numeric characters for driving a standard seven-segment LED display have been devised for Omega station identification. The circuit could replace the system now being used in Ohio University's Omega receivers, which lights one of eight LED's to signify the Omega time slot being received. The letters A through H, representing the Omega stations, can be read directly from the seven-segment display.

Smith, R. E.↗

Digital phase shifter synchronizes local oscillators

Digital phase-shifting network is used as synchronous frequency multiplier for applications such as phase-locking two signals that may differ in frequency. Circuit has various phase-shift capability. Possible applications include data-communication systems and hybrid digital/analog phase-locked loops.

Ali, S. M.↗

The development of an interim generalized gate logic software simulator

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

Mcgough, J. G.↗

Gas Flow Detection System

This system provides a portable means to detect gas flow through a thin-walled tube without breaking into the tubing system. The flow detection system was specifically designed to detect flow through two parallel branches of a manifold with only one inlet and outlet, and is a means for verifying a space shuttle program requirement that saves time and reduces the risk of flight hardware damage compared to the current means of requirement verification. The prototype Purge Vent and Drain Window Cavity Conditioning System (PVD WCCS) Flow Detection System consists of a heater and a temperature-sensing thermistor attached to a piece of Velcro to be attached to each branch of a WCCS manifold for the duration of the requirement verification test. The heaters and thermistors are connected to a shielded cable and then to an electronics enclosure, which contains the power supplies, relays, and circuit board to provide power, signal conditioning, and control. The electronics enclosure is then connected to a commercial data acquisition box to provide analog to digital conversion as well as digital control. This data acquisition box is then connected to a commercial laptop running a custom application created using National Instruments LabVIEW. The operation of the PVD WCCS Flow Detection System consists of first attaching a heater/thermistor assembly to each of the two branches of one manifold while there is no flow through the manifold. Next, the software application running on the laptop is used to turn on the heaters and to monitor the manifold branch temperatures. When the system has reached thermal equilibrium, the software application s graphical user interface (GUI) will indicate that the branch temperatures are stable. The operator can then physically open the flow control valve to initiate the test flow of gaseous nitrogen (GN2) through the manifold. Next, the software user interface will be monitored for stable temperature indications when the system is again at thermal equilibrium with the test flow of GN2. The temperature drop of each branch from its "no flow" stable temperature peak to its stable "with flow" temperature will allow the operator to determine whether a minimum level of flow exists. An alternative operation has the operator turning on the software only long enough to record the ambient temperature of the tubing before turning on the heaters and initiating GN2 flow. The stable temperature of the heated tubing with GN2 flow is then compared with the ambient tubing temperature to determine if flow is present in each branch. To help quantify the level of flow in the manifolds, each branch will be bench calibrated to establish its thermal properties using the flow detection system and different flow rates. These calibration values can then be incorporated into the software application to provide more detailed flow rate information.

Moss, Thomas↗

Hardware in the Loop Testing of an Iodine-Fed Hall Thruster

CUBESATS are relatively new spacecraft platforms that are typically deployed from a launch vehicle as a secondary payload,1 providing low-cost access to space for a wide range of end-users. These satellites are comprised of building blocks having dimensions of 10x10x10 cm cu and a mass of 1.33 kg (a 1-U size). While providing low-cost access to space, a major operational limitation is the lack of a propulsion system that can fit within a CubeSat and is capable of executing high delta v maneuvers. This makes it difficult to use CubeSats on missions requiring certain types of maneuvers (i.e. formation flying, spacecraft rendezvous). Recently, work has been performed investigating the use of iodine as a propellant for Hall-effect thrusters (HETs) 2 that could subsequently be used to provide a high specific impulse path to CubeSat propulsion. Iodine stores as a dense solid at very low pressures, making it acceptable as a propellant on a secondary payload. It has exceptionally high ρIsp (density times specific impulse), making it an enabling technology for small satellite near-term applications and providing the potential for systems-level advantages over mid-term high power electric propulsion options. Iodine flow can also be thermally regulated, subliming at relatively low temperature ( less than100 C) to yield I2 vapor at or below 50 torr. At low power, the measured performance of an iodine-fed HET is very similar to that of a state-of-the-art xenon-fed thruster. Just as importantly, the current-voltage discharge characteristics of low power iodine-fed and xenon-fed thrusters are remarkably similar, potentially reducing development and qualifications costs by making it possible to use an already-qualified xenon-HET PPU in an iodine-fed system. Finally, a cold surface can be installed in a vacuum test chamber on which expended iodine propellant can deposit. In addition, the temperature doesn't have to be extremely cold to maintain a low vapor pressure in the vacuum chamber (it is under 10(exp -6) torr at -75 C), making it possible to 'cryopump' the propellant with lower-cost recirculating refrigerant-based systems as opposed to using liquid nitrogen or low temperature gaseous helium cryopanels. In the present paper, we describe testing performed using an iodine-fed 200 W Hall thruster mounted to a thrust stand and operated in conjunction with MSFCs Small Projects Rapid Integration and Test Environment (SPRITE) Portable Hardware In the Loop (PHIL) hardware. This work is performed in support of the iodine satellite (iSAT) project, which aims to fly a 200-W iodine-fed thruster on a 12-U CubeSat. The SPRITE PHIL hardware allows a given vehicle to do a checkout of its avionics algorithm by allowing it to monitor and feed data to simulated sensors and effectors in a digital environment. These data are then used to determine the attitude of the vehicle and a separate computer is used to interpret the data set and visualize it using a 3D graphical interface. The PHIL hardware allows the testing of the vehicles bus by providing 'real' hardware interfaces (in the case of this test a real RS422 bus) and specific components can be modeled to show their interactions with the avionics algorithm (e.g. a thruster model). For the iSAT project the PHIL is used to visualize the operating cycle of the thruster and the subsequent effect this thrusting has on the attitude of the satellite over a given period of time. The test is controlled using software running on an Andrews Space Cortex 160 flight computer. This computer is the current baseline for a full iSAT mission. While the test could be conducted with a lab computer and software, the team chose to exercise the propulsion system with a representative CubeSat-class computer. For purposes of this test, the "flight" software monitored the propulsion and PPU systems, controlled operation of the thruster, and provided thruster state data to the PHIL simulation. Commands to operate the thruster were initiated from an operator's workstation outside the vacuum chamber and passed through the Cortex 160 to exercise portions of the flight avionics. Two custom-designed pieces of electronics hardware have been designed to operate the propellant feed system. One piece of hardware is an auxiliary board that controls a latch valve, proportional flow control valves (PFCVs) and valve heaters as well as measuring pressures, temperatures and PFCV feedback voltage. An onboard FPGA provides a serial link for issuing commands and manages all lower level input-output functions. The other piece of hardware is a power distribution board, which accepts a standard bus voltage input and converts this voltage into all the different current-voltage types required to operate the auxiliary board. These electronics boards are located in the vacuum chamber near the thruster, exposing this hardware to both the vacuum and plasma environments they would encounter during a mission, with these components communicating to the flight computer through an RS-422 interface. The auxiliary board FPGA provides a 28V MOSFET switch circuit with a 20ms pulse to open or close the iodine propellant feed system latch valve. The FPGA provides a pulse width modulation (PWM) signal to a DC/DC boost converter to produce the 12-120V needed for control of the proportional flow control valve. There are eight MOSFET-switched heating circuits in the system. Heaters are 28V and located in the latch valve, PFCV, propellant tank and propellant feed lines. Both the latch valve and PFCV have thermistors built into them for temperature monitoring. There are also seven resistance temperature device (RTD) circuits on the auxiliary board that can be used to measure the propellant tank and feedline temperatures. The signals are conditioned and sent to an analog to digital converter (ADC), which is directly commanded and controlled by the FPGA.

Polzin, Kurt A.↗