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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 829 records · Page 46
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

The design of radiation-hardened ICs for space - A compendium of approaches

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Kerns, Sherra E.↗
NASA NTRS1989

A programmable CCD driver circuit for multiphase CCD operation

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Ewin, Audrey J.↗
NASA NTRS1990

Upper-Bound Estimates Of SEU in CMOS

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Edmonds, Larry D.↗
NASA NTRS1990

Exact Chord-Length Distribution For SEU Calculations

Computed rates of SEU's more accurate. Exact integral chord-length distribution derived for use in calculations of rates of single-event upsets (SEU's) (changes in logic states) caused by impingement of cosmic rays or other ionizing radiation on electronic logic circuits.

Buehler, Martin G.↗
NASA NTRS1990

Temperature Dependence Of Single-Event Effects

Report describes experimental study of effects of temperature on vulnerability of integrated-circuit memories and other electronic logic devices to single-event effects - spurious bit flips or latch-up in logic state caused by impacts of energetic ions. Involved analysis of data on 14 different device types. In most cases examined, vulnerability to these effects increased or remain constant with temperature.

Coss, James R.↗
NASA NTRS1989

Simulation of shuttle flight control system structural interaction with RMS deployed payloads

A simulation of the system made up of the Orbiter, Remote Manipulator System (RMS), and payload grappled by the RMS was completed. The simulation was used to study the stability of this overall system when its attitude is under control of the Orbiter's on-orbit Flight Control System (FCS). The simulation was also used to study the dynamics of the system when the RMS and its associated command software are in active control of the relative Orbiter to payload position and orientation. The simulation models all of the following elements: RMS boom bending (represented by two cubic bending models); RMS boom torsion; RMS joint gearbox compliance (represented by a non-linear wind-up model); flexibility at the RMS to Orbiter interface; flexibility at the RMS to payload interface; joint motor dynamics; joint servo-loop dynamics; RMS on-board computer command logic; data transfer delays between the RMS sensor and the RMS on-board computer and between the RMS on-board computer and RMS joint servos; on-orbit flight control nonlinear control logic; and the Reaction Control System (both Primary and Vernier) jet forces and moments.

Turnball, Joe↗
NASA NTRS1989

Stress in dilute suspensions

Generally, two types of theory are used to describe the field equations for suspensions. The so-called postulated equations are based on the kinetic theory of mixtures, which logically should give reasonable equations for solutions. The basis for the use of such theory for suspensions is tenuous, though it at least gives a logical path for mathematical arguments. It has the disadvantage that it leads to a system of equations which is underdetermined, in a sense that can be made precise. On the other hand, the so-called averaging theory starts with a determined system, but the very process of averaging renders the resulting system underdetermined. A third type of theory is proposed in which the kinetic theory of gases is used to motivate continuum equations for the suspended particles. This entails an interpretation of the stress in the particles that is different from the usual one. Classical theory is used to describe the motion of the suspending medium. The result is a determined system for a dilute suspension. Extension of the theory to more concentrated systems is discussed.

Passman, Stephen L.↗
NASA NTRS1989

Avoiding a maneuvering aircraft with TCAS

The present investigation was carried out in NASA's Man-Vehicle Systems Research Facility B 727 simulator because of the need for veridical aircraft response. Pilot performance was measured in testing TCAS II after an avoidance maneuver has been initiated. A proposed change to the system will cause the TCAS II to issue a subsequent maneuver. This maneuver may be an increase in climb or descent rate from 1500 to 2500 ft/min, or a change from a climb to a descent or a descent to a climb. Three questions were addressed: (1) can the pilot detect the change in the maneuver advisory, (2) can the pilot respond promptly and accurately to the new advisory, and (3) can the maneuver be performed in the normal operating envelope of the aircraft. The reaction times found in the study suggest that pilots are able to respond within the two seconds targeted by the TCAS logic. The pilot performance data were used to modify the TCAS II logic to reflect actual pilot performance. This will result in a safe and appropriate maneuver selection in the rare instance when the conflicting aircraft maneuvers, and by doing so invalidates the initial maneuver issued by the collision avoidance system.

Chappell, Sheryl L.↗
NASA NTRS1990

Analysis of faults in an N-version software experiment

The authors have conducted a large-scale experiment in N-version programming. A total of 27 versions of a program were prepared independently from the same specification at two universities. The results of executing the versions revealed that the versions were individually extremely reliable but that the number of input cases in which more than one failed was substantially more than would be expected if they were statistically independent. After the versions had been executed, the failures of each version were examined and the associated faults located. The analysis showed that in some cases the programmers made equivalent logical errors, indicating that some parts of the problem were simply more difficult than others. The authors also found cases in which apparently different logical errors yielded faults that caused statistically correlated failures, indicating that there are special cases in the input space that present difficulty in various parts of the solution. A formal model is presented to explain this phenomenon. It appears that minor differences in the software development environment would not have a major impact in reducing the incidence of faults that cause correlated failures.

Brilliant, Susan S.↗
NASA NTRS1990

A bit-serial VLSI array processing chip for image processing

An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to mask PEs individually. A modified grid interconnection scheme allows each PE to communicate with each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1-micron CMOS design contains over 1.1 x 10 to the 6th transistors on an 11.0 x 11.7-mm die.

Heaton, Robert↗
NASA NTRS1991

Preventing Aim At An Undesired Target

Electronic system controls changes in orientation of optical instrument. Slew-control system includes avoidance-control logic, which overrides slew-control error generator when line of sight of instrument comes within cone of avoidance around line of sight to Sun. Normal slewing trajectory interrupted by avoidance-control logic, which computes actuator torques taking line of sight around cone of avoidance. Used to protect delicate photodetectors in servocontrolled infrared spectrometer or imaging instrument against damage occurring if instrument aimed at Sun or another excessively bright object.

Goodzeit, Neil E.↗
NASA NTRS1991

Trinary Associative Memory Would Recognize Machine Parts

Trinary associative memory combines merits and overcomes major deficiencies of unipolar and bipolar logics by combining them in three-valued logic that reverts to unipolar or bipolar binary selectively, as needed to perform specific tasks. Advantage of associative memory: one obtains access to all parts of it simultaneously on basis of content, rather than address, of data. Consequently, used to exploit fully parallelism and speed of optical computing.

Liu, Hua-Kuang↗
NASA NTRS1991

Sign-And-Magnitude Up/Down Counter

Magnitude-and-sign counter includes conventional up/down counter for magnitude part and special additional circuitry for sign part. Negative numbers indicated more directly. Counter implemented by programming erasable programmable logic device (EPLD) or programmable logic array (PLA). Used in place of conventional up/down counter to provide sign and magnitude values directly to other circuits.

Cole, Steven W.↗
NASA NTRS1990

Digitized synchronous demodulator

A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors.

Woodhouse, Christopher E.↗
NASA NTRS1991

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Smith, Edwyn D.↗
NASA NTRS1991

An area model for on-chip memories and its application

An area model suitable for comparing data buffers of different organizations and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage. The model gave less than 10 percent error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches, direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas, both direct-mapped and set-associative caches perform better than fully associative caches.

Mulder, Johannes M.↗
NASA NTRS1991

Aerospace plane guidance using time-scale decomposition - A geometric approach

A method is proposed for developing the necessary guidance logic to steer single-stage vehicles into orbit. The minimum-fuel ascent problem is first considered to analyze the effects of dynamic pressure, acceleration, and heating constraints on guidance systems to thereby develop the guidance logic. The optimal solution consists of behavior with two time scales, and the control law is used to develop near-optimal guidance. The solution uses the slow manifold to delineate the control for minimum-fuel reduced-order trajectory and a separate control for tracking the optimal reduced-order trajectory. A family of fast manifolds is then employed to resolve the tracking problem via the feedback linearization methodology from nonlinear geometric control theory. The two-time-scale decomposition is found to produce a near-optimal ascent by tracking the applicable state-constraint boundary, as well as to simplify the control-design task.

Van Buren, Mark A.↗
NASA NTRS1991

Approximate reasoning-based learning and control for proximity operations and docking in space

A recently proposed hybrid-neutral-network and fuzzy-logic-control architecture is applied to a fuzzy logic controller developed for attitude control of the Space Shuttle. A model using reinforcement learning and learning from past experience for fine-tuning its knowledge base is proposed. Two main components of this approximate reasoning-based intelligent control (ARIC) model - an action-state evaluation network and action selection network are described as well as the Space Shuttle attitude controller. An ARIC model for the controller is presented, and it is noted that the input layer in each network includes three nodes representing the angle error, angle error rate, and bias node. Preliminary results indicate that the controller can hold the pitch rate within its desired deadband and starts to use the jets at about 500 sec in the run.

Berenji, Hamid R.↗