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NASA NTRS1988

Estimating Rates Of Single-Event Upsets

Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.

Zoutendyk, John A.↗

NASA NTRS1992

Recent advances in superconducting-mixer simulations

Over the last few years, considerable progress have been made in the development of techniques for fabricating high-quality superconducting circuits, and this success, together with major advances in the theoretical understanding of quantum detection and mixing at millimeter and submillimeter wavelengths, has made the development of CAD techniques for superconducting nonlinear circuits an important new enterprise. For example, arrays of quasioptical mixers are now being manufactured, where the antennas, matching networks, filters and superconducting tunnel junctions are all fabricated by depositing niobium and a variety of oxides on a single quartz substrate. There are no adjustable tuning elements on these integrated circuits, and therefore, one must be able to predict their electrical behavior precisely. This requirement, together with a general interest in the generic behavior of devices such as direct detectors and harmonic mixers, has lead us to develop a range of CAD tools for simulating the large-signal, small-signal, and noise behavior of superconducting tunnel junction circuits.

Withington, S.↗

NASA NTRS1995

A new RF package suitable for aeronautical commercial and DSCS satellite applications

Higher levels of integration through the use of GaAs and silicon MMIC devices, a die-cast housing, and the reduction of the number of subassemblies has enabled a large reduction of the size and weight of the electronics package for commercial and military satellite communications. This paper presents an electronics architecture and hardware that utilizes many new integrated circuits and design techniques, and allows flexibility for future satellite frequency changes and expansion. Key features of the radio are extended C-band, InSat, Defense Satellite Communications System (DSCS), and Ku-band coverage options; 70 (or 140) MHz transponder bandwidth or L-band block bandwidth IFs; integrated RS-232 control through local handheld terminal or remote computer; remote control of crystal reference oscillator for aging and temperature compensation; integrated 2 or 5 watt solid-state power amplifiers (SSPA); optional integrated solid-state booster amplifiers to 40 watts; optional external amplifiers to 100 watts; integral beacon tracking with second integrated downcoverter for antenna positioning; radio, including low-noise block converter (LNB) and SSPA, weighs 8.5 kg and measures 32 x 23 x 16.5 cm; environmentally ruggedized for -40 to +60 C; O-ring sealed for waterproofing; passive (convection) cooling; and simple cabling and installation, with a single cable between radio and LNB, and two cables between radio and IF interface. The small size and light weight of the radio make it ideal for mounting on stabilized antenna platforms (gyroscopic or servo). Several input power options (110 or 220 VAC; +48, +12, or -24 VDC) facilitate operation on multiple platforms.

Hamilton, Robert J., Jr.↗

NASA NTRS2005

Alumina or Semiconductor Ribbon Waveguides at 30 to 1,000 GHz

Ribbon waveguides made of alumina or of semiconductors (Si, InP, or GaAs) have been proposed as low-loss transmission lines for coupling electronic components and circuits that operate at frequencies from 30 to 1,000 GHz. In addition to low losses (and a concomitant ability to withstand power levels higher than would otherwise be possible), the proposed ribbon waveguides would offer the advantage of compatibility with the materials and structures now commonly incorporated into integrated circuits. Heretofore, low-loss transmission lines for this frequency range have been unknown, making it necessary to resort to designs that, variously, place circuits and components to be coupled in proximity of each other and/or provide for coupling via free space through bulky and often lossy optical elements. Even chip-to-chip interconnections have been problematic in this frequency range. Metal wave-guiding structures (e.g., microstriplines and traditional waveguides) are not suitable for this frequency range because the skin depths of electromagnetic waves in this frequency range are so small as to give rise to high losses. Conventional rod-type dielectric waveguide structures are also not suitable for this frequency range because dielectric materials, including ones that exhibit ultralow losses at lower frequencies, exhibit significant losses in this frequency range. Unlike microstripline structures or metallic waveguides, the proposed ribbon waveguides would be free of metal and would therefore not be subject to skin-depth losses. Moreover, although they would be made of materials that are moderately lossy in the frequency range of interest, the proposed ribbon waveguides would cause the propagating electromagnetic waves to configure themselves in a manner that minimizes losses.

Yeh, Cavour↗

NASA NTRS2006

Modified Coaxial Probe Feeds for Layered Antennas

In a modified configuration of a coaxial probe feed for a layered printed-circuit antenna (e.g., a microstrip antenna), the outer conductor of the coaxial cable extends through the thickness of at least one dielectric layer and is connected to both the ground-plane conductor and a radiator-plane conductor. This modified configuration simplifies the incorporation of such radio-frequency integrated circuits as power dividers, filters, and low-noise amplifiers. It also simplifies the design and fabrication of stacked antennas with aperture feeds.

Fink, Patrick W.↗

NASA NTRS2020

High Temperature Electronics for Venus Surface Applications: A Summary of Recent Technical Advances

This white paper has a technical focus meant to provide background to those unfamiliar with the challenges of high temperature electronics, and an understanding of why new surface mission concepts are now viable for Venus and other applications. It describes that, for the first time, high temperature electronics have been developed to enable a paradigm change in extended duration Venus surface exploration. This white paper concentrates on the advances made in Silicon Carbide (SiC) integrated circuit (IC) electronics that have matured to a state where a simple long-life scientific probe is feasible for Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, 60 days in high-fidelity simulated Venus surface conditions chamber, and have been integrated and demonstrated with prototype long-lived scientific observation sensor technology. Continued maturation of these needed high temperature electronics and sensors is ongoing in the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system including sensor control and operation, signal processing, power management, and communications in the early part of the 2020’s. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements. Other IC development efforts include high temperature memory, terrestrial based characterization of volcanic magma, and development of a simple microprocessor. This electronics has also shown to have exceptionally high radiation tolerance, and thus have relevance for a broad range of solar system exploration. Although presently at the level of complexity of 1970-1980 silicon-based electronics, such electronics can enable breakthroughs in Venus planetary exploration akin to 1970s-launched planetary exploration successes (such as Viking and Voyager).

High temperature Electronics↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

High temperature↗

NASA NTRS2003

Development of a 1K x 1K GaAs QWIP Far IR Imaging Array

In the on-going evolution of GaAs Quantum Well Infrared Photodetectors (QWIPs) we have developed a 1,024 x 1,024 (1K x1K), 8.4-9 microns infrared focal plane array (FPA). This 1 megapixel detector array is a hybrid using the Rockwell TCM 8050 silicon readout integrated circuit (ROIC) bump bonded to a GaAs QWIP array fabricated jointly by engineers at the Goddard Space Flight Center (GSFC) and the Army Research Laboratory (ARL). The finished hybrid is thinned at the Jet Propulsion Lab. Prior to this development the largest format array was a 512 x 640 FPA. We have integrated the 1K x 1K array into an imaging camera system and performed tests over the 40K-90K temperature range achieving BLIP performance at an operating temperature of 76K (f/2 camera system). The GaAs array is relatively easy to fabricate once the superlattice structure of the quantum wells has been defined and grown. The overall arrays costs are currently dominated by the costs associated with the silicon readout since the GaAs array fabrication is based on high yield, well-established GaAs processing capabilities. In this paper we will present the first results of our 1K x 1K QWIP array development including fabrication methodology, test data and our imaging results.

Jhabvala, M.↗

NASA NTRS1999

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗

NASA NTRS2011

Infrared-Bolometer Arrays with Reflective Backshorts

Integrated circuits that incorporate square arrays of superconducting-transition- edge bolometers with optically reflective backshorts are being developed for use in image sensors in the spectral range from far infrared to millimeter wavelengths. To maximize the optical efficiency (and, thus, sensitivity) of such a sensor at a specific wavelength, resonant optical structures are created by placing the backshorts at a quarter wavelength behind the bolometer plane. The bolometer and backshort arrays are fabricated separately, then integrated to form a single unit denoted a backshort-under-grid (BUG) bolometer array. In a subsequent fabrication step, the BUG bolometer array is connected, by use of single-sided indium bump bonding, to a readout device that comprises mostly a superconducting quantum interference device (SQUID) multiplexer circuit. The resulting sensor unit comprising the BUG bolometer array and the readout device is operated at a temperature below 1 K. The concept of increasing optical efficiency by use of backshorts at a quarter wavelength behind the bolometers is not new. Instead, the novelty of the present development lies mainly in several features of the design of the BUG bolometer array and the fabrication sequence used to implement the design. Prior to joining with the backshort array, the bolometer array comprises, more specifically, a square grid of free-standing molybdenum/gold superconducting-transition-edge bolometer elements on a 1.4- m-thick top layer of silicon that is part of a silicon support frame made from a silicon-on-insulator wafer. The backshort array is fabricated separately as a frame structure that includes support beams and contains a correspond - ing grid of optically reflective patches on a single-crystal silicon substrate. The process used to fabricate the bolometer array includes standard patterning and etching steps that result in the formation of deep notches in the silicon support frame. These notches are designed to interlock with the support beams on the backshort-array structure to provide structural support and precise relative positioning. The backshort-array structure is inserted in the silicon support frame behind the bolometer array, and the notches in the frame serve to receive the support beams of the backshort-array structure and thus determine the distance between the backshort and bolometer planes. The depth of the notches and, thus, the distance between the backshort and bolometer planes, can be tailored to a value between 25 to 300 m adjusting only a few process steps. The backshort array is designed so as not to interfere with the placement of indium bumps for subsequent indium bump-bonding to the multiplexing readout circuitry

Miller, Timothy M.↗

NASA NTRS2003

Electronic Components and Circuits for Extreme Temperature Environments

Planetary exploration missions and deep space probes require electrical power management and control systems that are capable of efficient and reliable operation in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures will not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures; thereby reducing system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior and tolerance in the electrical and thermal properties of semiconductor and dielectric materials at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial-off-the-shelf as well as developed components that are being characterized include switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being investigated for potential use in low temperature applications. An overview of the NASA Glenn Research Center Low Temperature Electronic Program will be presented in this paper. A description of the low temperature test facilities along with selected data obtained through in-house component and circuit testing will also be discussed. Ongoing research activities that are being performed in collaboration with various organizations will also be presented.

Patterson, Richard L.↗

NASA NTRS2002

Cryogenic Electronics Being Developed for Space Operation

Planetary exploration missions and deep space probes require electrical power management and control systems that can operate efficiently and reliably in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units to maintain the surrounding temperature of the onboard electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures would not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures. Thereby, such electronics would reduce system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results because semiconductor and dielectric materials have better behavior and tolerance in their electrical and thermal properties at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center is focusing on the research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and in deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial off-the-shelf as well as developed components that are being characterized include semiconductor switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, dc-dc converters, operational amplifiers, and oscillators are also being investigated for potential use in low-temperature applications. For example, the output response of an advanced oscillator at room temperature and at -190 C is shown. Most oscillators can operate at temperatures down to only -55 C. It can be seen that, for this oscillator, the low temperature of -196 C changed the leading and trailing edges of the oscillator pulses by producing overshoot. The research and development efforts performed under the Low Temperature Electronics Program at Glenn are being carried out through collaboration with other Government agencies, industrial and aerospace companies, and academia. The program supports missions as well as technology development efforts at NASA's Goddard Space Flight Center and Langley Research Center, and the Jet Propulsion Laboratory.

Patterson, Richard L.↗

NASA NTRSDate not supplied

A Brief Overview of Relevant Silicon Carbide Electronics and Sensor Development for Long Duration Venus Surface Exploration

This presentation concentrates on the potential of long duration Venus surface missions, and the role of Silicon Carbide (SiC) electronics and sensor advancements in such exploration. For example, SiC integrated circuit (IC) electronics have matured to a state where a simple long-life scientific probe is feasible for extended Venus surface operations. These electronics have been demonstrated for more than a year at 500˚C, and 60 days in high-fidelity simulated Venus surface conditions [1-2]. Further, high temperature chemical sensing technology, including SiC-based gas sensors, integrated with SiC electronics can enable future exploration of the Venus surface atmosphere [3]. Continued maturation of these high temperature electronics and sensors has been part of the Long-Lived In-Situ Solar System Explorer (LLISSE) project to provide an operational system for in situ exploration of the Venus surface up to 60 days [4]. A key focus of this work includes increasing the complexity and decreasing the power consumption of the ICs which will pave the way to enhanced capabilities, such as long-duration Venus seismic measurements and other mission capabilities currently under development. This is in parallel to work expanding the capabilities of the sensor technology to provide science measurements on the Venus surface. This presentation will give an overview of possible extended duration Venus surface exploration and some of the SiC-based technologies that can enable this exploration.

high temperature Venus surface electronics sensors↗

NASA NTRS2016

Open Source Radiation Hardened by Design Technology

The proposed technology allows use of the latest microcircuit technology with lowest power and fastest speed, with minimal delay and engineering costs, through new Radiation Hardened by Design (RHBD) techniques that do not require extensive process characterization, technique evaluation and re-design at each Moore's Law generation. The separation of critical node groups is explicitly parameterized so it can be increased as microcircuit technologies shrink. The technology will be open access to radiation tolerant circuit vendors. INNOVATION: This technology would enhance computation intensive applications such as autonomy, robotics, advanced sensor and tracking processes, as well as low power applications such as wireless sensor networks. OUTCOME / RESULTS: 1) Simulation analysis indicates feasibility. 2)Compact voting latch 65 nanometer test chip designed and submitted for fabrication -7/2016. INFUSION FOR SPACE / EARTH: This technology may be used in any digital integrated circuit in which a high level of resistance to Single Event Upsets is desired, and has the greatest benefit outside low earth orbit where cosmic rays are numerous.

Shuler, Robert↗

NASA NTRS2008

Inertial Orientation Trackers with Drift Compensation

A class of inertial-sensor systems with drift compensation has been invented for use in measuring the orientations of human heads (and perhaps other, similarly sized objects). These systems can be designed to overcome some of the limitations of prior orientation-measuring systems that are based, variously, on magnetic, optical, mechanical-linkage, and acoustical principles. The orientation signals generated by the systems of this invention could be used for diverse purposes, including controlling head-orientation-dependent virtual reality visual displays or enabling persons whose limbs are paralyzed to control machinery by means of head motions. The inventive concept admits to variations too numerous to describe here, making it necessary to limit this description to a typical system, the selected aspects of which are illustrated in the figure. A set of sensors is mounted on a bracket on a band or a cap that gently but firmly grips the wearer s head to be tracked. Among the sensors are three drift-sensitive rotationrate sensors (e.g., integrated-circuit angular- rate-measuring gyroscopes), which put out DC voltages nominally proportional to the rates of rotation about their sensory axes. These sensors are mounted in mutually orthogonal orientations for measuring rates of rotation about the roll, pitch, and yaw axes of the wearer s head. The outputs of these rate sensors are conditioned and digitized, and the resulting data are fed to an integrator module implemented in software in a digital computer. In the integrator module, the angular-rate signals are jointly integrated by any of several established methods to obtain a set of angles that represent approximately the orientation of the head in an external, inertial coordinate system. Because some drift is always present as a component of an angular position computed by integrating the outputs of angular-rate sensors, the orientation signal is processed further in a drift-compensator software module.

Foxlin, Eric M.↗

NASA NTRS2011

Architecture for a 1-GHz Digital RADAR

An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

Mallik, Udayan↗

NASA NTRS2011

Fault-Tolerant, Radiation-Hard DSP

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Czajkowski, David↗