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At least 811 records · Page 45

Holographic Compact Disk Read-Only Memories

Compact disk read-only memories (CD-ROMs) of proposed type store digital data in volume holograms instead of in surface differentially reflective elements. Holographic CD-ROM consist largely of parts similar to those used in conventional CD-ROMs. However, achieves 10 or more times data-storage capacity and throughput by use of wavelength-multiplexing/volume-hologram scheme.

Liu, Tsuen-Hsi↗

New double-byte error-correcting codes for memory systems

Error-correcting or error-detecting codes have been used in the computer industry to increase reliability, reduce service costs, and maintain data integrity. The single-byte error-correcting and double-byte error-detecting (SbEC-DbED) codes have been successfully used in computer memory subsystems. There are many methods to construct double-byte error-correcting (DBEC) codes. In the present paper we construct a class of double-byte error-correcting codes, which are more efficient than those known to be optimum, and a decoding procedure for our codes is also considered.

Feng, Gui-Liang↗

Ensuring correct rollback recovery in distributed shared memory systems

Distributed shared memory (DSM) implemented on a cluster of workstations is an increasingly attractive platform for executing parallel scientific applications. Checkpointing and rollback techniques can be used in such a system to allow the computation to progress in spite of the temporary failure of one or more processing nodes. This paper presents the design of an independent checkpointing method for DSM that takes advantage of DSM's specific properties to reduce error-free and rollback overhead. The scheme reduces the dependencies that need to be considered for correct rollback to those resulting from transfers of pages. Furthermore, in-transit messages can be recovered without the use of logging. We extend the scheme to a DSM implementation using lazy release consistency, where the frequency of dependencies is further reduced.

Janssens, Bob↗

Control of Thermal Deflection, Panel Flutter and Acoustic Fatigue at Elevated Temperatures Using Shape Memory Alloys

The High Speed Civil Transport (HSCT) will have to be designed to withstand high aerodynamic load at supersonic speeds (panel flutter) and high acoustic load (acoustic or sonic fatigue) due to fluctuating boundary layer or jet engine acoustic pressure. The thermal deflection of the skin panels will also alter the vehicle's configuration, thus it may affect the aerodynamic characteristics of the vehicle and lead to poor performance. Shape memory alloys (SMA) have an unique ability to recover large strains completely when the alloy is heated above the characteristic transformation (austenite finish T(sub f)) temperature. The recovery stress and elastic modulus are both temperature dependent, and the recovery stress also depends on the initial strain. An innovative concept is to utilize the recovery stress by embedding the initially strained SMA wire in a graphite/epoxy composite laminated panel. The SMA wires are thus restrained and large inplane forces are induced in the panel at elevated temeperatures. By embedding SMA in composite panel, the panel becomes much stiffer at elevated temperatures. That is because the large tensile inplane forces induced in the panel from the SMA recovery stress. A stiffer panel would certainly yield smaller dynamic responses.

Mei, Chuh↗

Smart Material Demonstrators Based on Shape Memory Alloys and Electroceramics

This paper describes the development and characterization of two technology demonstrators that were produced under the auspices of an ARPA sponsored smart materials synthesis and processing effort. The ARPA Smart Materials and Synthesis (SMS) Program was a 2 year, $10M partnership led by Martin Marietta Laboratories - Baltimore and included Lockheed Missiles & Space Co., NRL, AVX Corp., Martin Marietta Astronautics Groups, BDM Federal, Inc., Virginia Tech, Clemson, University of Maryland, Denver University, and The Johns Hopkins University. In order to demonstrate the usefulness of magnetron sputtered shape memory foil and the manufacturability of reliable, reproducible electrostrictive actuators, the team designed a broadband active vibration cancellation device for suppressing the vibration load on delicate instruments and precision pointing devices mounted on orbiting satellites and spacecraft. The results of extensive device characterization and bench testing are discussed. Initial simulation results show excellent control authority and amplitude attenuation over the range of anticipated disturbance frequencies. The SMS Team has also developed an active 1-3 composite comprising micro-electrostrictive actuators embedded in a polymeric matrix suitable for underwater applications such as sonar quieting and listening arrays, and for medical imaging. Follow-on programs employing these technologies are also described.

Cooke, Arther V.↗

Improved Damage Resistant Composite Materials Incorporating Shape Memory Alloys

Metallic shape memory alloys (SMA) such as nitinol have unique shape recovery behavior and mechanical properties associated with a material phase change that have been used in a variety of sensing and actuation applications. Recent studies have shown that integrating nitinol-SMA actuators into composite materials increases the composite material's functionality. Hybrid composites of conventional graphite/epoxy or glass/epoxy and nitinol-SMA elements can perform functions in applications where monolithic composites perform inadequately. One such application is the use of hybrid composites to function both in load bearing and armor capacities. While monolithic composites with high strength-to-weight ratios function efficiently as loadbearing structures, because of their brittle nature, impact loading can cause significant catastrophic damage. Initial composite failure modes such as delamination and matrix cracking dissipate some impact energy, but when stress exceeds the composite's ultimate strength, fiber fracture and material perforation become dominant. One of the few methods that has been developed to reduce material perforation is hybridizing polymer matrix composites with tough kevlar or high modulus polyethynylene plies. The tough fibers increase the impact resistance and the stiffer and stronger graphite fibers carry the majority of the load. Similarly, by adding nitinol-SMA elements that absorb impact energy through the stress-induced martensitic phase transformation, the composites' impact perforation resistance can be greatly enhanced. The results of drop-weight and high velocity gas-gun impact testing of various composite materials will be presented. The results demonstrate that hybridizing composites with nitinol-SMA elements significantly increases perforation resistance compared to other traditional toughening elements. Inspection of the composite specimens at various stages of perforation by optical microscope illustrates the mechanisms by which perforation is initiated. Results suggest that the out-of-plane transverse shear properties of the composite and nitinol elements have a significant effect on the perforation resistance. Applications that can utilize the hybrid composites effectively will also be presented with the experimental studies.

Paine, Jeffrey S. N.↗

Impact of Load Balancing on Unstructured Adaptive Grid Computations for Distributed-Memory Multiprocessors

The computational requirements for an adaptive solution of unsteady problems change as the simulation progresses. This causes workload imbalance among processors on a parallel machine which, in turn, requires significant data movement at runtime. We present a new dynamic load-balancing framework, called JOVE, that balances the workload across all processors with a global view. Whenever the computational mesh is adapted, JOVE is activated to eliminate the load imbalance. JOVE has been implemented on an IBM SP2 distributed-memory machine in MPI for portability. Experimental results for two model meshes demonstrate that mesh adaption with load balancing gives more than a sixfold improvement over one without load balancing. We also show that JOVE gives a 24-fold speedup on 64 processors compared to sequential execution.

Biswas, Rupak↗

Impact of Load Balancing on Unstructured Adaptive Grid Computations for Distributed-Memory Multiprocessors

The computational requirements for an adaptive solution of unsteady problems change as the simulation progresses. This causes workload imbalance among processors on a parallel machine which, in turn, requires significant data movement at runtime. We present a new dynamic load-balancing framework, called JOVE, that balances the workload across all processors with a global view. Whenever the computational mesh is adapted, JOVE is activated to eliminate the load imbalance. JOVE has been implemented on an IBM SP2 distributed-memory machine in MPI for portability. Experimental results for two model meshes demonstrate that mesh adaption with load balancing gives more than a sixfold improvement over one without load balancing. We also show that JOVE gives a 24-fold speedup on 64 processors compared to sequential execution.

Sohn, Andrew↗

Reducing Interprocessor Dependence in Recoverable Distributed Shared Memory

Checkpointing techniques in parallel systems use dependency tracking and/or message logging to ensure that a system rolls back to a consistent state. Traditional dependency tracking in distributed shared memory (DSM) systems is expensive because of high communication frequency. In this paper we show that, if designed correctly, a DSM system only needs to consider dependencies due to the transfer of blocks of data, resulting in reduced dependency tracking overhead and reduced potential for rollback propagation. We develop an ownership timestamp scheme to tolerate the loss of block state information and develop a passive server model of execution where interactions between processors are considered atomic. With our scheme, dependencies are significantly reduced compared to the traditional message-passing model.

Janssens, Bob↗

An Efficient Multiblock Method for Aerodynamic Analysis and Design on Distributed Memory Systems

The work presented in this paper describes the application of a multiblock gridding strategy to the solution of aerodynamic design optimization problems involving complex configurations. The design process is parallelized using the MPI (Message Passing Interface) Standard such that it can be efficiently run on a variety of distributed memory systems ranging from traditional parallel computers to networks of workstations. Substantial improvements to the parallel performance of the baseline method are presented, with particular attention to their impact on the scalability of the program as a function of the mesh size. Drag minimization calculations at a fixed coefficient of lift are presented for a business jet configuration that includes the wing, body, pylon, aft-mounted nacelle, and vertical and horizontal tails. An aerodynamic design optimization is performed with both the Euler and Reynolds Averaged Navier-Stokes (RANS) equations governing the flow solution and the results are compared. These sample calculations establish the feasibility of efficient aerodynamic optimization of complete aircraft configurations using the RANS equations as the flow model. There still exists, however, the need for detailed studies of the importance of a true viscous adjoint method which holds the promise of tackling the minimization of not only the wave and induced components of drag, but also the viscous drag.

Reuther, James↗

Analysis of a Memory Device Failure

The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

Nicolas, David P.↗

Experimental Results and Issues on Equalization for Nonlinear Memory Channel: Pre-Cursor Enhanced Ram-DFE Canceler

This thesis investigates the effects of the High Power Amplifier (HPA) and the filters over a satellite or telemetry channel. The Volterra series expression is presented for the nonlinear channel with memory, and the algorithm is based on the finite-state machine model. A RAM-based algorithm operating on the receiver side, Pre-cursor Enhanced RAM-FSE Canceler (PERC) is developed. A high order modulation scheme , 16-QAM is used for simulation, the results show that PERC provides an efficient and reliable method to transmit data on the bandlimited nonlinear channel. The contribution of PERC algorithm is that it includes both pre-cursors and post-cursors as the RAM address lines, and suggests a new way to make decision on the pre-addresses. Compared with the RAM-DFE structure that only includes post- addresses, the BER versus Eb/NO performance of PERC is substantially enhanced. Experiments are performed for PERC algorithms with different parameters on AWGN channels, and the results are compared and analyzed. The investigation of this thesis includes software simulation and hardware verification. Hardware is setup to collect actual TWT data. Simulation on both the software-generated data and the real-world data are performed. Practical limitations are considered for the hardware collected data. Simulation results verified the reliability of the PERC algorithm. This work was conducted at NMSU in the Center for Space Telemetering and Telecommunications Systems in the Klipsch School of Electrical and Computer Engineering Department.

Yuan, Lu↗

Corporate Memory and Spacecraft Course Development

The Florida Space Grant Consortium (FSGC) entered into a cooperative agreement with NASA's Kennedy Space Center (KSC) to manage two programs, (1) Corporate Memory and (2) Spacecraft Course Development. The FSGC, with its central office at the University of Florida, administered these programs. In conjunction with KSC, the FGSC was responsible for the release of the Request for Proposals (RFP's) and its distribution to all its affiliates. FSGC received the applications, forwarded them to KSC for evaluations, and awarded grants to the institutions chosen by KSC.

Source record↗

Active Vibration Control of Elastic Beam by Means of Shape Memory Alloy Layers

The mathematical model of a flexible beam covered with shape memory alloy (SMA) layers is presented. The SMA layers are used as actuators, which are capable of changing their elastic modulus and recovery stress, thus changing the natural frequency of, and adjusting the excitation to, the vibrating beam. The frequency factor variation as a function of SMA Young's modulus, SMA layer thickness and beam thickness is discussed. Also control of the beam employing an optimal linear control law is evaluated. The control results indicate how the system reacts to various levels of excitation input through the non-homogeneous recovery shear term of the governing differential equation.

Chen, Q.↗

Dynamic Load Balancing for Adaptive Computations on Distributed-Memory Machines

Dynamic load balancing is central to adaptive mesh-based computations on large-scale parallel computers. The principal investigator has investigated various issues on the dynamic load balancing problem under NASA JOVE and JAG rants. The major accomplishments of the project are two graph partitioning algorithms and a load balancing framework. The S-HARP dynamic graph partitioner is known to be the fastest among the known dynamic graph partitioners to date. It can partition a graph of over 100,000 vertices in 0.25 seconds on a 64- processor Cray T3E distributed-memory multiprocessor while maintaining the scalability of over 16-fold speedup. Other known and widely used dynamic graph partitioners take over a second or two while giving low scalability of a few fold speedup on 64 processors. These results have been published in journals and peer-reviewed flagship conferences.

Source record↗

UNICON Laser Memory: Interlaced Codes for Multi-burst-Error Correction

Interlaced binary BCH codes are described for multiple-burst-error correction for the UNICON 690 laser memory. Other multiple-burst-error-correcting codes, such as Reed-Solomon codes and Product codes, are also briefly mentioned. In particular, an interlaced (31, 21) t = 2 BCH code is selected as an outer code for UNICON double-burst-error correction. This code is shortened to (26,16) and interlaced to degree X = 16. Decoding is implemented by table lookup. This method not only avoids all computations in GF(2(exp 5)), it also offers a decoding time of less than 1 ps. The inner code is an existing (80,64) Fire code capable of correcting a single-burst error of length b less than or equal to 6.

Lim, R. S.↗

Radiation Effects on Advanced Flash Memories

Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.

Nguyen, D. N.↗

MLP: A Parallel Programming Alternative to MPI for New Shared Memory Parallel Systems

Recent developments at the NASA AMES Research Center's NAS Division have demonstrated that the new generation of NUMA based Symmetric Multi-Processing systems (SMPs), such as the Silicon Graphics Origin 2000, can successfully execute legacy vector oriented CFD production codes at sustained rates far exceeding processing rates possible on dedicated 16 CPU Cray C90 systems. This high level of performance is achieved via shared memory based Multi-Level Parallelism (MLP). This programming approach, developed at NAS and outlined below, is distinct from the message passing paradigm of MPI. It offers parallelism at both the fine and coarse grained level, with communication latencies that are approximately 50-100 times lower than typical MPI implementations on the same platform. Such latency reductions offer the promise of performance scaling to very large CPU counts. The method draws on, but is also distinct from, the newly defined OpenMP specification, which uses compiler directives to support a limited subset of multi-level parallel operations. The NAS MLP method is general, and applicable to a large class of NASA CFD codes.

Taft, James R.↗