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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 811 records · Page 45
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

A memory-driven mapping algorithm for heterogeneous systems

mpibind is a memory-driven algorithm to map parallel hybrid applications to the underlying hardware resources transparently, efficiently, and portably. There are two fundamental aspects of this algorithm. First, unlike existing mappings, its primary design point is the memory system. Compute elements are selected based on the identified memory components and not vice versa. Second, it embodies a global awareness of hybrid programming abstractions as well as heterogeneous devices.

Leon Borja, EdgarA↗
DOE OSTI2015

Limited-memory adaptive snapshot selection for proper orthogonal decomposition

Reduced order models are useful for accelerating simulations in many-query contexts, such as optimization, uncertainty quantification, and sensitivity analysis. However, offline training of reduced order models can have prohibitively expensive memory and floating-point operation costs in high-performance computing applications, where memory per core is limited. To overcome this limitation for proper orthogonal decomposition, we propose a novel adaptive selection method for snapshots in time that limits offline training costs by selecting snapshots according an error control mechanism similar to that found in adaptive time-stepping ordinary differential equation solvers. The error estimator used in this work is related to theory bounding the approximation error in time of proper orthogonal decomposition-based reduced order models, and memory usage is minimized by computing the singular value decomposition using a single-pass incremental algorithm. Results for a viscous Burgers’ test problem demonstrate convergence in the limit as the algorithm error tolerances go to zero; in this limit, the full order model is recovered to within discretization error. The resulting method can be used on supercomputers to generate proper orthogonal decomposition-based reduced order models, or as a subroutine within hyperreduction algorithms that require taking snapshots in time, or within greedy algorithms for sampling parameter space.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

zorder-lib: Library API for Z-Order Memory Layout

This document describes the motivation for, elements of, and use of the zorder-lib, a library API that implements organization of and access to data in memory using either a-order (also known as "row-major" order) or z-order memory layouts. The primary motivation for this work is to improve the performance of many types of data- intensive codes by increasing both spatial and temporal locality of memory accesses. The basic idea is that the cost associated with accessing a datum is less when it is nearby in either space or time.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗
DOE OSTI2015

zorder-lib: Library API for Z-Order Memory Layout

This document describes the motivation for, elements of, and use of the zorder-lib, a library API that implements organization of and access to data in memory using either a-order (also known as “row-major” order) or z-order memory layouts. The primary motivation for this work is to improve the performance of many types of data-intensive codes by increasing both spatial and temporal locality of memory accesses. The basic idea is that the cost associated with accessing a datum is less when it is nearby in either space or time.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

GentenMPI: Distributed Memory Sparse Tensor Decomposition

GentenMPl is a toolkit of sparse canonical polyadic (CP) tensor decomposition algorithms that is designed to run effectively on distributed-memory high-performance computers. Its use of distributed-memory parallelism enables it to efficiently decompose tensors that are too large for a single compute node's memory. GentenMPl leverages Sandia's decades-long investment in the Trilinos solver framework for much of its parallel-computation capability. Trilinos contains numerical algorithms and linear algebra classes that have been optimized for parallel simulation of complex physical phenomena. This work applies these tools to the data science problem of sparse tensor decomposition. In this report, we describe the use of Trilinos in GentenMPl, extensions needed for sparse tensor decomposition, and implementations of the CP-ALS (CP via alternating least squares) and GCP-SGD (generalized CP via stochastic gradient descent) sparse tensor decomposition algorithms. We show that GentenMPl can decompose sparse tensors of extreme size, e.g., a 12.6-terabyte tensor on 8192 computer cores. We demonstrate that the Trilinos backbone provides good strong and weak scaling of the tensor decomposition algorithms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Probabilistic Nanomagnetic Memories for Uncertain and Robust Machine Learning

This project evaluated the use of emerging spintronic memory devices for robust and efficient variational inference schemes. Variational inference (VI) schemes, which constrain the distribution for each weight to be a Gaussian distribution with a mean and standard deviation, are a tractable method for calculating posterior distributions of weights in a Bayesian neural network such that this neural network can also be trained using the powerful backpropagation algorithm. Our project focuses on domain-wall magnetic tunnel junctions (DW-MTJs), a powerful multi-functional spintronic synapse design that can achieve low power switching while also opening the pathway towards repeatable, analog operation using fabricated notches. Our initial efforts to employ DW-MTJs as an all-in-one stochastic synapse with both a mean and standard deviation didn’t end up meeting the quality metrics for hardware-friendly VI. In the future, new device stacks and methods for expressive anisotropy modification may make this idea still possible. However, as a fall back that immediately satisfies our requirements, we invented and detailed how the combination of a DW-MTJ synapse encoding the mean and a probabilistic Bayes-MTJ device, programmed via a ferroelectric or ionically modifiable layer, can robustly and expressively implement VI. This design includes a physics-informed small circuit model, that was scaled up to perform and demonstrate rigorous uncertainty quantification applications, up to and including small convolutional networks on a grayscale image classification task, and larger (Residual) networks implementing multi-channel image classification. Lastly, as these results and ideas all depend upon the idea of an inference application where weights (spintronic memory states) remain non-volatile, the retention of these synapses for the notched case was further interrogated. These investigations revealed and emphasized the importance of both notch geometry and anisotropy modification in order to further enhance the endurance of written spintronic states. In the near future, these results will be mapped to effective predictions for room temperature and elevated operation DW-MTJ memory retention, and experimentally verified when devices become available.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2025

New Results on Communication- and Memory-Aware Load Balancing Model and Algorithms

While load balancing in distributed-memory computing has been well-studied, we present an innovative approach to this problem: a unified, reduced-order model that combines three key components to describe “work” in a distributed system: computation, communication, and memory. Our model enables an optimizer to explore complex tradeoffs in task placement, such as augmented parallelism, at the expense of data replication increasing memory usage. We propose a fully distributed, heuristic-based load balancing optimization algorithm, and demonstrate that it quickly finds close-to-optimal solutions. We formalize the complex optimization problem as a mixed-integer linear program, and compare it to our strategy. Finally, we show that when applied to an electromagnetics code, our approach obtains up to 2.3x speedups for the imbalanced execution.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Loss of Mitochondrial Tusc2/Fus1 Triggers a Brain Pro-Inflammatory Microenvironment and Early Spatial Memory Impairment

Brain pathological changes impair cognition early in disease etiology. There is an urgent need to understand aging-linked mechanisms of early memory loss to develop therapeutic strategies and prevent the development of cognitive impairment. Tusc2 is a mitochondrial-resident protein regulating Ca 2+ fluxes to and from mitochondria impacting overall health. We previously reported that Tusc2 –/– female mice develop chronic inflammation and age prematurely, causing age- and sex-dependent spatial memory deficits at 5 months old. Therefore, we investigated Tusc2-dependent mechanisms of memory impairment in 4-month-old mice, comparing changes in resident and brain-infiltrating immune cells. Interestingly, Tusc2 –/– female mice demonstrated a pro-inflammatory increase in astrocytes, expression of IFN-γ in CD4 + T cells and Granzyme-B in CD8 + T cells. We also found fewer FOXP3 + T-regulatory cells and Ly49G + NK and Ly49G + NKT cells in female Tusc2 –/– brains, suggesting a dampened anti-inflammatory response. Moreover, Tusc2 –/– hippocampi exhibited Tusc2- and sex-specific protein changes associated with brain plasticity, including mTOR activation, and Calbindin and CamKII dysregulation affecting intracellular Ca2 + dynamics. Overall, the data suggest that dysregulation of Ca 2+ -dependent processes and a heightened pro-inflammatory brain microenvironment in Tusc2 –/– mice could underlie cognitive impairment. Thus, strategies to modulate the mitochondrial Tusc2- and Ca 2+ - signaling pathways in the brain should be explored to improve cognitive health.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2016

CENTRAL ENGINE MEMORY OF GAMMA-RAY BURSTS AND SOFT GAMMA-RAY REPEATERS

Gamma-ray bursts (GRBs) are bursts of γ-rays generated from relativistic jets launched from catastrophic events such as massive star core collapse or binary compact star coalescence. Previous studies suggested that GRB emission is erratic, with no noticeable memory in the central engine. Here we report a discovery that similar light curve patterns exist within individual bursts for at least some GRBs. Applying the Dynamic Time Warping method, we show that similarity of light curve patterns between pulses of a single burst or between the light curves of a GRB and its X-ray flare can be identified. This suggests that the central engine of at least some GRBs carries “memory” of its activities. We also show that the same technique can identify memory-like emission episodes in the flaring emission in soft gamma-ray repeaters (SGRs), which are believed to be Galactic, highly magnetized neutron stars named magnetars. Such a phenomenon challenges the standard black hole central engine models for GRBs, and suggest a common physical mechanism behind GRBs and SGRs, which points toward a magnetar central engine of GRBs.

79 ASTRONOMY AND ASTROPHYSICS↗
NASA NTRS1972

Dual redundant core memory systems

Electronic memory system consisting of series redundant drive switch circuits, triple redundant majority voted memory timing functions, and two data registers to provide functional dual redundancy is described. Signal flow through the circuits is illustrated and equence of events which occur within the memory system is explained.

Hull, F. E.↗
NASA NTRS1972

Apollo guidance, navigation and control: Guidance system operations plans for manned LM earth orbital and lunar missions using Program COLOSSUS 3. Section 7: Erasable memory programs

Erasable-memory programs (EMPs) designed for the guidance computers used in the command (CMC) and lunar modules (LGC) are described. CMC programs are designated COLOSSUS 3, and the associated EMPs are identified by a three-digit number beginning with 5. LGC programs are designated LUMINARY 1E, and the associated EMPs are identified, with one exception, by a three-digit number beginning with 1. The exception is EMP 99. The EMPs vary in complexity from a simple flagbit setting to a long and intricate logical structure. They all, however, cause the computer to behave in a way not intended in the original design of the programs; they accomplish this off-nominal behavior by some alteration of erasable memory to interface with existing fixed-memory programs to effect a desired result.

Hamilton, M. H.↗
NASA NTRS1972

Sequential behavior and its inherent tolerance to memory faults.

Representation of a memory fault of a sequential machine M by a function mu on the states of M and the result of the fault by an appropriately determined machine M(mu). Given some sequential behavior B, its inherent tolerance to memory faults can then be measured in terms of the minimum memory redundancy required to realize B with a state-assigned machine having fault tolerance type tau and fault tolerance level t. A behavior having maximum inherent tolerance is exhibited, and it is shown that behaviors of the same size can have different inherent tolerance.

Meyer, J. F.↗
NASA NTRS1972

Development of a monolithic ferrite memory array

The results of the development and testing of ferrite monolithic memory arrays are presented. This development required the synthesis of ferrite materials having special magnetic and physical characteristics and the development of special processes; (1) for making flexible sheets (laminae) of the ferrite composition, (2) for embedding conductors in ferrite, and (3) bonding ferrite laminae together to form a monolithic structure. Major problems encountered in each of these areas and their solutions are discussed. Twenty-two full-size arrays were fabricated and fired during the development of these processes. The majority of these arrays were tested for their memory characteristics as well as for their physical characteristics and the results are presented. The arrays produced during this program meet the essential goals and demonstrate the feasibility of fabricating monolithic ferrite memory arrays by the processes developed.

Heckler, C. H., Jr.↗
NASA NTRS1973

A simulation model for a memory organization for a multiprocessor.

A model for a memory organization for a multiprocessor with look-ahead and interleaved multimodule main memory is presented. The model is used to determine the extent of look-ahead and depth of interleaving that provide the most prolific speed match between processors and main memory.

Eubank, J. B.↗
NASA NTRS1974

Plated wire memory subsystem

The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

Carpenter, K. H.↗
NASA NTRS1974

Magnetic bubble domain memories

Some attractive features of Bubble Domain Memory and its relation to existing technologies are discussed. Two promising applications are block access mass memory and tape recorder replacement. The required chip capabilities for these uses are listed, and the specifications for a block access mass memory designed to fit between core and HPT disk are presented. A feasibility model for a tape recorder replacement is introduced.

Ypma, J. E.↗
NASA NTRS1975

Main memory unit

The development of a main memory unit (MMU) for the space ultrareliable module computer (SUMC) model HTC is discussed. The design, fabrication, and test of basic memory modules (BMM) which were to be used in the design and construction of the MMU are described. The BMM was designed from state-of-the-art technologies which included large scale integration devices mounted and interconnected on a substrate to form a functional module to be utilized in the MMU development. A SUMC memory system design study is discussed which addressed itself to the BMM design and analysis to be conducted to determine the most efficient organization of the BMM in order to establish such modularity features as: word length expandability without redesign, high reliability, and fault tolerance. One MMU was designed, fabricated, tested, and delivered which will be electrical and mechanically compatible with the hybrid technology computer (HTC) model of the SUMC family of computers. The MMU will contain a storage capacity of 8196 36 bit words which includes a parity bit for each 8 bit byte of data.

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