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Results for “hardware efficiency”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 811 records · Page 45
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Using Likwid and Byfl to Benchmark Hardware Performance

This paper outlines a benchmarking study conducted during my internship at LANL, focusing on CPU (Computer Processing Unit) and program performance assessment. The primary goal was to gather memory access data using three methods across five polybench kernels The data gathered would then be used to compare and contrast to one another and calculate operational intensity for performance comparisons. Benchmarking tools like Byfl and Likwid were employed, with Byfl offering hardware-independent data through LLVM compiler communication and Likwid directly interacting with computer hardware. The study considered various benchmarking factors, including optimization levels, Big O notation ((n)), CPU diversity and specific kernel equations. Big O notation was utilized to simplify code complexity, with detailed breakdwons of operations and memory components for each polybench application. Specific O(n) equations enabled nuanced kernel compariosns, facilitating the identification of performance variations. CPU efficiency assessments were conducted using Likwid tests on two CPUs. The central focus on code optimization aimed at achieving higher speeds and reduced memory usage through streamlined code. Future work propsoes creating a roofline model, synthesizing benchmarking data into a comprehensive data graph to assist in optimizing code and improving hardware performance. The potential impact on the laboratory or national mission was underscored, emphasizing the importance of optimizing applications and hardware to conserve resources and accelerate program execution. The specific relevance to LANL’s operations in math-intensive fields such as Nuclear Fission, Space Exploration, and Nanotechnology highlights the necessity of efficient benchmarking for resource conservation and proram speed. Overall, this study contributes to the understanding of CPU and program performance, providing insights for future optimization efforts in a laboratory setting

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Real-time Implementation of a Dual-Active-Bridge Based Multi-Level Photovoltaic Converter

Silicon-carbide based, multi-level converters with dual-active-bridge (DAB) are getting attention for medium voltage, direct grid-connected, utility-scale photovoltaic (PV) applications due to their higher efficiency and power density. To de-risk complex control development for these high-voltage and high-power inverters, hardware-in-the-loop techniques are often required. Due to the high switching frequency and the large number of power electronic switches, off-the-shelf, real-time simulation tools are not yet fully developed for this application, even with FPGA-based simulators. To address this, a new co-simulation approach in FPGA is presented that utilizes Time-Stamped Bridge (TSB) for the higher frequency converters along with detailed fixed conductance based discrete device simulation of the rest of the circuit. A complex DAB-based PV converter with maximum switching frequency of 50 kHz is successfully simulated in real-time in the FPGA and the results are compared with offline simulation results. A controller hardware-in-the-loop (CHIL) platform is developed to demonstrate real-time, closed-loop test results for this DAB-based PV converter.

Dong, Zerui↗
DOE OSTI2022

Time-Efficient Qudit Gates through Incremental Pulse Re-seeding

Current efforts to build quantum computers focus mainly on the two-state qubit, which often involves suppressing readily-available higher states. In this work, we break this abstraction and synthesize short-duration control pulses for gates on generalized d-state qudits. We present Incremental Pulse Reseeding, a practical scheme to guide optimal control software to the lowest-duration pulse by iteratively seeding the optimizer with previous results. We find a near-linear relationship between Hilbert space dimension and gate duration through explicit pulse optimization for one- and two-qudit gates on transmons. Furthermore, our results suggest that qudit operations are much more efficient than previously expected in the practical regime of interest and have the potential to significantly increase the computational power of current hardware.

pulse synthesis↗
DOE OSTI2023

FFTX-IRIS: Towards Performance Portability and Heterogeneity for SPIRAL Generated Code

FFTX-IRIS is a dynamic system to efficiently utilize novel heterogeneous platforms. This system links two next-generation frameworks, FFTX and IRIS, to navigate the complexity of different hardware architectures. FFTX provides a runtime code generation framework for high-performance Fast Fourier Transform kernels. IRIS runtime provides portability and multi-device heterogeneity, allowing computation on any available compute resource. Together, FFTX-IRIS enables code generation, seamless portability, and performance without user involvement. We show the design of the FFTX-IRIS system along with an evaluation of various small FFT benchmarks. We also demonstrate multi-device heterogeneity of FFTX-IRIS with a larger stencil application.

Rao, Sanil↗
NASA NTRS1971

ALSEP data management.

Nine million measurements a day are transmitted from each functional ALSEP on the moon and continuously collected on earth for use in long-term scientific analysis. Periodically, this massive flow of intricate data is examined on a real-time basis to evaluate ALSEP performance and to study the need for new commands to any of the ALSEP systems. A worldwide complex of facilities and personnel has the challenging task of efficient and timely data processing and dissemination. This paper describes facility characteristics and support activities and details certain constraints imposed on ALSEP hardware design by data handling requirements. The highlights of the first two years of lunar data management are reviewed.

Murtaugh, C. R.↗
NASA NTRS1988

Description of an oscillating flow pressure drop test rig

A test rig designed to generate heat exchanger pressure drop information under oscillating flow conditions is described. This oscillating flow rig is based on a variable stroke and variable frequency linear drive motor. A frequency capability of 120 hertz and a mean test pressure up to 15 mPA (2200 psi) allows for testing at flow conditions found in modern high specific power Stirling engines. An important design feature of this rig is that it utilizes a single close coupled dynamic pressure transducer to measure the pressure drop across the test sample. This eliminates instrumentation difficulties associated with the pressure sensing lines common to differential pressure transducers. Another feature of the rig is that it utilizes a single displacement piston. This allows for testing of different sample lengths and configurations without hardware modifications. All data acquisition and reduction for the rig is performed with a dedicated personal computer. Thus the overall system design efficiently integrates the testing and data reduction procedures. The design methodology and details of the test rig is described.

Wood, J. Gary↗
NASA NTRS1988

Description of an oscillating flow pressure drop test rig

A test rig designed to generate heat exchanger pressure drop information under oscillating flow conditions is described. This oscillating flow rig is based on a variable stroke and variable frequency linear drive motor. A frequency capability of 120 hertz and a mean test pressure up to 15 mPA (2200 psi) allows for testing at flow conditions found in modern high specific power Stirling engines. An important design feature of this rig is that it utilizes a single close coupled dynamic pressure transducer to measure the pressure drop across the test sample. This eliminates instrumentation difficulties associated with the pressure sensing lines common to differential pressure transducers. Another feature of the rig is that it utilizes a single displacement piston. This allows for testing of different sample lengths and configurations without hardware modifications. All data acquisition and reduction for the rig is performed with a dedicated personal computer. Thus the overall system design efficiently integrates the testing and data reduction procedures. The design methodology and details of the test rig are described.

Wood, J. Gary↗
NASA NTRS1990

On-board switching and processing

Findings from NASA's space electronics division's (SED's) advanced systems studies related to future communications satellite services that will require onboard switching and processing technology are reviewed. SED's digital signal switching and processing technology program is reviewed. This program responds to specific systems technology development needs for enabling commercial development of future satellite services. The technologies include: modulators, demodulators, and forward error-correction hardware for space- and ground-based applications; onboard information switching and processing, onboard network control, and health monitoring; and cost-efficient ground terminals. The in-house systems integration, test, and evaluation (SITE) project, which includes a laboratory testbed for evaluating technology in a simulated systems environment, is reviewed.

Harrold, Joseph L.↗
NASA NTRS1990

Advanced multiple access concepts in mobile satellite systems

Some multiple access strategies for Mobile Satellite Systems (MSS) are discussed. These strategies were investigated in the context of three separate studies conducted for the International Maritime Satellite Organization (INMARSAT) and the European Space Agency (ESA). Satellite-Switched Frequency Division Multiple Access (SS-FDMA), Code Division Multiple Access (CDMA), and Frequency-Addressable Beam architectures are addressed, discussing both system and technology aspects and outlining advantages and drawbacks of either solution with associated relevant hardware issues. An attempt is made to compare the considered option from the standpoint of user terminal/space segment complexity, synchronization requirements, spectral efficiency, and interference rejection.

Ananasso, Fulvio↗
NASA NTRS1997

Multi-Axis Fluidic Thrust Vectoring of a Supersonic Jet Using Counterflow

The most common techniques currently used to efficiently vector supersonic jets require external flaps and or pivoting devices. Fluidic thrust vectoring using counterflow eliminates the need for such complex hardware. Thus, the promise of decreases in both weight and drag as well as increased maneuverability makes this technique an attractive alternative. This technique has been successfully employed to achieve single axis fluidic thrust vectoring of a Mach 2 rectangular jet. To better compete with contemporary systems the current study extends this technique to multi-axis thrust vectoring of a Mach 2 diamond-shaped jet by applying counterflow to one of its four sides. To evaluate the performance of this technique the Planar Laser Scattering (PLS) technique is used to show the continuous vectoring of the diamond jet up to 20 degrees. Also, cross-stream PLS images are acquired to show the vectoring can be achieved off all four surfaces of the diamond jet.

Barber, Edward L.↗
NASA NTRS1997

Free-Swinging Failure Tolerance for Robotic Manipulators

Under this GSRP fellowship, software-based failure-tolerance techniques were developed for robotic manipulators. The focus was on failures characterized by the loss of actuator torque at a joint, called free-swinging failures. The research results spanned many aspects of the free-swinging failure-tolerance problem, from preparing for an expected failure to discovery of postfailure capabilities to establishing efficient methods to realize those capabilities. Developed algorithms were verified using computer-based dynamic simulations, and these were further verified using hardware experiments at Johnson Space Center.

English, James↗
NASA NTRS1997

Free-Swinging Failure Tolerance for Robotic Manipulators

Under this GSRP fellowship, software-based failure-tolerance techniques were developed for robotic manipulators. The focus was on failures characterized by the loss of actuator torque at a joint, called free-swinging failures. The research results spanned many aspects of the free-swinging failure-tolerance problem, from preparing for an expected failure to discovery of postfailure capabilities to establishing efficient methods to realize those capabilities. Developed algorithms were verified using computer-based dynamic simulations, and these were further verified using hardware experiments at Johnson Space Center.

English, James↗
NASA NTRS2001

A Unique Software System For Simulation-to-Flight Research

"Simulation-to-Flight" is a research development concept to reduce costs and increase testing efficiency of future major aeronautical research efforts at NASA. The simulation-to-flight concept is achieved by using common software and hardware, procedures, and processes for both piloted-simulation and flight testing. This concept was applied to the design and development of two full-size transport simulators, a research system installed on a NASA B-757 airplane, and two supporting laboratories. This paper describes the software system that supports the simulation-to-flight facilities. Examples of various simulation-to-flight experimental applications were also provided.

Chung, Victoria I.↗
DOE OSTI2021

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operationson Spatial Accelerators

To meet the extreme compute demands for deep learning across commercial and scientific applications, dataflow accelerators are becoming increasingly popular. While these“domain-specific” accelerators are not fully programmable like CPUs and GPUs, they retain varying levels of flexibility with respect to data orchestration, i.e., dataflow and tiling optimizations to enhance efficiency. There are several challenges when designing new algorithms and mapping approaches to execute the algorithms for a target problem on new hardware. Previous works have addressed these challenges individually. To address this challenge as a whole, in this work, we present an HW-SW co-design ecosystem for spatial accelerators called Union within the popular MLIR compiler infrastructure. Our framework allows exploring different algorithms and their mappings on several accelerator cost models. Union also includes a plug-and-play library of accelerator cost models and mappers which can easily be extended. The algorithms and accelerator cost models are connected via a novel mapping abstraction that captures the map space of spatial accelerators which can be systematically pruned based on constraints from the hardware, workload, and mapper. We demonstrate the value of Union for the community with several case studies which examine offloading different tensor operations (CONV/GEMM/Tensor Contraction) on diverse accelerator architectures using different mapping schemes.

Jeong, Geonhwa↗
DOE OSTI2025

Surrogate Neural Architecture Codesign Package (SNAC-Pack)

Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neural Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment. SNAC-Pack combines Neural Architecture Codesign's multi-stage search capabilities with the Resource Utilization and Latency Estimator, enabling multi-objective optimization across accuracy, FPGA resource utilization, and latency without requiring time-intensive synthesis for each candidate model. We demonstrate SNAC-Pack on a high energy physics jet classification task, achieving 63.84% accuracy with resource estimation. When synthesized on a Xilinx Virtex UltraScale+ VU13P FPGA, the SNAC-Pack model matches baseline accuracy while maintaining comparable resource utilization to models optimized using traditional BOPs metrics. This work demonstrates the potential of hardware-aware neural architecture search for resource-constrained deployments and provides an open-source framework for automating the design of efficient FPGA-accelerated models.

Weitz, Jason [UC, San Diego] (ORCID:00090004631535↗
DOE OSTI2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers

The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).

Castellana, Vito G.↗
DOE OSTI2021

High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers

The increased need for efficient ways to implement domain-specific accelerators is driving design methodologies towards the use of abstractions higher than the Register Transfer Level (RTL). In this scenario, High Level Synthesis (HLS) plays a significant role by enabling the automatic generation of custom hardware accelerators starting from high level descriptions (e.g., C code). Conventional HLS tools exploit parallelism mostly at the Instruction Level (ILP). They statically schedule the input specifications, and build centralized Finite State Machine (FSM) controllers. However, aggressive exploitation of ILP in many applications has diminishing returns and, usually, centralized approaches do not efficiently exploit coarser parallelism because FSMs are inherently serial. In this paper we present a HLS framework able to synthesize applications that, beside ILP, also expose Task Level Parallelism (TLP). An application can expose TLP through annotations that identify the parallel functions (i.e., tasks). To generate accelerators that efficiently execute concur- rent tasks, we need to solve several issues: devise a mechanism to support concurrent execution flows, exploit memory parallelism, and manage synchronization. To support concurrent execution flows, we introduce a novel adaptive controller. The adaptive controller is composed of a set of interacting control elements that independently manage the execution of a single operation or function call. These control elements check dependencies and resource constraints at runtime, enabling as soon as possible execution. To support parallel access to shared memories and synchronization, we introduce a novel Hierarchical Memory Interface (HMI). With respect to previous solutions, the proposed interface supports multi-ported memories and atomic memory operations, which commonly occur in parallel programming. Our framework can generate the hardware implementation of C functions by employing two different approaches, depending on its characteristics. If a function exposes TLP, then the framework generates hardware implementations based on the adaptive controller. Otherwise, the framework implements the function by exploiting a more conventional FSM approach, which is optimized for ILP exploitation. We evaluate our framework on a set of parallel applications, and show substantial performance improvements (average speedup of 4.7) with limited area over- heads (average area increase of 5.48 times).

Castellana, Vito G.↗
NASA NTRSDate not supplied

Controls for Electrified Aircraft Propulsion

Advanced electrified aircraft propulsion (EAP) concepts with integrated power, propulsion, and thermal systems require the development of equally sophisticated controllers to fly safe and efficient missions. Hybrid electric aircraft utilize electric machines mechanically coupled to the engine shafts to extract and insert power for a variety of purposes. Additionally, electric machines may drive propulsive fans pulling from a combination of on-board energy storage devices and engine extracted power. NASA’s investment in hybrid electric aircraft hardware-in-the-loop testing enables controls research on representative engine models using a novel emulation and scaling methodology. High-voltage, high-power electrical powertrain presents several technical risks at altitude. High-power requires high efficiency to minimize losses. Superconducting electric machines and power distribution research at NASA has identified key challenges with potential controls solutions. These risks necessitate the development of controllers robust to model uncertainty, disturbances, and fault conditions. System health management and fault detection schemes play an important role in a multi-layer controls approach that utilizes a supervisor which oversees inner loops for the highly coupled power, propulsion, and thermal systems. Such a supervisory controller enables coordinates energy transfer between engines, energy storage devices, electric machines, propulsors, and heat exchangers. Existing methods have shown an improvement in engine operability using the hybrid electric powertrain.

Halle E Buescher↗