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At least 811 records · Page 45

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NASA NTRS1993

Diversity reception for advanced multi-satellite networks: A CDMA approach

Diversity reception for Synchronous CDMA (S-CDMA) is introduced and analyzed. A Gaussian co-channel synchronous and asynchronous interference approximation is derived to evaluate the effects on the system bit error rate. Numerical results are provided for a simple mobile communication system where the signals transmitted by two distinct satellites in visibility are coherently combined by a three fingers Rake receiver. A second example showing performance of an integrated ground/satellite single frequency network for digital audio broadcasting is presented. Results show the capacity advantage of utilizing S-CDMA in combination with diversity reception.

Colzi, E.↗

NASA NTRS1994

Bounds and Simulation Results of 32-ary and 64-ary Quadrature Amplitude Modulation for Broadband-ISDN via Satellite

Union bounds and Monte Carlo simulation Bit-Error-Rate (BER) performance results are presented for various 32-ary and 64-ary Quadrature Amplitude Modulation (QAM) schemes. Filtered and unfiltered modulation formats are compared for the best packing arrangement in peak power limited systems. It is verified that circular constellations which populate as many symbols as possible at the peak magnitude offer the best performance. For example: a 32-ary QAM scheme based on concentric circles offers about 1.05 dB better peak power improvement at a BER of 10(exp -6) over the scheme optimized for average power using triangular symbol packing. This peak power improvement increases to 1.25 dB for comparable 64-ary QAM schemes. This work serves as a precursor to determine the feasibility of a combined modem/codec that can accommodate Broadband Integrated Services Digital Network (B-ISDN) at a rate of 155.52 Mbps through typical transponder bandwidths of 36 MHz and 54 MHz.

Kifle, Muli↗

NASA NTRS1992

Advanced satellite communication system

The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.

Staples, Edward J.↗

NASA NTRS1994

Real-time sensor data validation

This report describes the status of an on-going effort to develop software capable of detecting sensor failures on rocket engines in real time. This software could be used in a rocket engine controller to prevent the erroneous shutdown of an engine due to sensor failures which would otherwise be interpreted as engine failures by the control software. The approach taken combines analytical redundancy with Bayesian belief networks to provide a solution which has well defined real-time characteristics and well-defined error rates. Analytical redundancy is a technique in which a sensor's value is predicted by using values from other sensors and known or empirically derived mathematical relations. A set of sensors and a set of relations among them form a network of cross-checks which can be used to periodically validate all of the sensors in the network. Bayesian belief networks provide a method of determining if each of the sensors in the network is valid, given the results of the cross-checks. This approach has been successfully demonstrated on the Technology Test Bed Engine at the NASA Marshall Space Flight Center. Current efforts are focused on extending the system to provide a validation capability for 100 sensors on the Space Shuttle Main Engine.

Bickmore, Timothy W.↗

NASA NTRS1993

A new tape product for optical data storage

A new tape product has been developed for optical data storage. Laser data recording is based on hole or pit formation in a low melting metallic alloy system. The media structure, sputter deposition process, and media characteristics, including write sensitivity, error rates, wear resistance, and archival storage are discussed.

Larsen, T. L.↗

NASA NTRS1994

Telecommunications end-to-end systems monitoring on TOPEX/Poseidon: Tools and techniques

The TOPEX/Poseidon Project Satellite Performance Analysis Team's (SPAT) roles and responsibilities have grown to include functions that are typically performed by other teams on JPL Flight Projects. In particular, SPAT Telecommunication's role has expanded beyond the nominal function of monitoring, assessing, characterizing, and trending the spacecraft (S/C) RF/Telecom subsystem to one of End-to-End Information Systems (EEIS) monitoring. This has been accomplished by taking advantage of the spacecraft and ground data system structures and protocols. By processing both the received spacecraft telemetry minor frame ground generated CRC flags and NASCOM block poly error flags, bit error rates (BER) for each link segment can be determined. This provides the capability to characterize the separate link segments, determine science data recovery, and perform fault/anomaly detection and isolation. By monitoring and managing the links, TOPEX has successfully recovered approximately 99.9 percent of the science data with an integrity (BER) of better than 1 x 10(exp 8). This paper presents the algorithms used to process the above flags and the techniques used for EEIS monitoring.

Calanche, Bruno J.↗

NASA NTRS1994

Tracking the Galileo spacecraft with the DSCC Galileo Telemetry prototype

On day of the year 062, 1994, a prototype of the Deep Space Communications Complex Galileo Telemetry subsystem successfully tracked and processed signals from the Galileo spacecraft, under fully suppressed-carrier modulation. The demonstration took place at Goldstone, employing the 70-m antenna and the 34-m high-efficiency antenna. This article presents the findings from that demonstration. Specific issues are the system performance in terms of signal-to-noise (SNR) degradation and the arraying gain. Validation of the test results is via symbol-error-rate measurement and the standard symbol SNR. The analysis is also extended to include characterization of the signal received from Galileo.

Pham, T. T.↗

NASA NTRS1995

Turbo codes for deep-space communications

Turbo codes were recently proposed by Berrou, Glavieux, and Thitimajshima, and it has been claimed these codes achieve near-Shannon-limit error correction performance with relatively simple component codes and large interleavers. A required E(b)/N(o) of 0.7 dB was reported for a bit error rate of 10(exp -5), using a rate 1/2 turbo code. However, some important details that are necessary to reproduce these results were omitted. This article confirms the accuracy of these claims, and presents a complete description of an encoder/decoder pair that could be suitable for deep-space applications, where lower rate codes can be used. We describe a new simple method for trellis termination, analyze the effect of interleaver choice on the weight distribution of the code, and introduce the use of unequal rate component codes, which yield better performance.

Divsalar, D.↗

NASA NTRS1995

Cochannel and Adjacent-Channel Interference in Nonlinear Minimum-Shift-Keyed Satellite System

The interference susceptibility of a serial-minimum-shift-keyed (SMSK) modulation system to an interfering signal transmitted through a satellite link with cascaded nonlinear elements was investigated through computer simulation. The satellite link evaluated in this study represented NASA's Advanced Communications Technology Satellite (ACTS) system. Specifically, nonlinear characteristics were used that had specified amplitude-modulation to amplitude-modulation and amplitude-modulation to phase-modulation transfer characteristics obtained from the actual ACTS hardware. Two measurement scenarios were analyzed: degradation of an MSK satellite link from cochannel interference and from adjacent-channel interference. Interference was evaluated in terms of the probability of bit error rate (BER) versus energy per bit over noise power density Eb/No.

Yu, John↗

NASA NTRS1994

Building an experience factory for maintenance

This paper reports the preliminary results of a study of the software maintenance process in the Flight Dynamics Division (FDD) of the National Aeronautics and Space Administration/Goddard Space Flight Center (NASA/GSFC). This study is being conducted by the Software Engineering Laboratory (SEL), a research organization sponsored by the Software Engineering Branch of the FDD, which investigates the effectiveness of software engineering technologies when applied to the development of applications software. This software maintenance study began in October 1993 and is being conducted using the Quality Improvement Paradigm (QIP), a process improvement strategy based on three iterative steps: understanding, assessing, and packaging. The preliminary results represent the outcome of the understanding phase, during which SEL researchers characterized the maintenance environment, product, and process. Findings indicate that a combination of quantitative and qualitative analysis is effective for studying the software maintenance process, that additional measures should be collected for maintenance (as opposed to new development), and that characteristics such as effort, error rate, and productivity are best considered on a 'release' basis rather than on a project basis. The research thus far has documented some basic differences between new development and software maintenance. It lays the foundation for further application of the QIP to investigate means of improving the maintenance process and product in the FDD.

Valett, Jon D.↗

NASA NTRS1995

Computer simulation results for PCM/PM/NRZ receivers in nonideal channels

This article studies, by computer simulations, the performance of deep-space telemetry signals that employ the pulse code modulation/phase modulation (PCM/PM) technique, using nonreturn-to-zero data, under the separate and combined effects of unbalanced data, data asymmetry, and a band-limited channel. The study is based on measuring the symbol error rate performance and comparing the results to the theoretical results presented in previous articles. Only the effects of imperfect carrier tracking due to an imperfect data stream are considered. The presence of an imperfect data stream (unbalanced and/or asymmetric) produces undesirable spectral components at the carrier frequency, creating an imperfect carrier reference that will degrade the performance of the telemetry system. Further disturbance to the carrier reference is caused by the intersymbol interference created by the band-limited channel.

Anabtawi, A.↗

NASA NTRS1995

Pseudocoherent Demodulation Of DPSK Radio Signals

Three schemes for pseudocoherent demodulation of differential-phase-shift keyed (DPSK) radio signals proposed for use in land-mobile/satellite communications. Enables fast reacquisition. Also amounts to compromise between two extremes of coherent demodulation and differentially coherent demodulation, for which bit-error rates greater than those of coherent demodulation by amounts corresponding to difference of about 1 dB in bit-energy/noise-energy ratio. Based on maximum-likelihood estimation and detection during N-symbol observation periods, where N integer typically chosen between 5 and 15.

Divsalar, Dariush↗

NASA NTRS1995

Hybrid system GMSK digital receiver implementation in real time

This paper is concerned with the design, simulation, and implementation of a hybrid system using the GMSK type of signal format for phase modulation and demodulation. The performance of the designed transceiver structure is evaluated using the bit error rate (BER) curves. The simulated system was also successfully implemented in real time.

Koshal, Sanjiv↗

NASA NTRS1995

Millennium Modem/Channelizer Special Test Equipment

A broadband modem/channelizer test set developed by NASA Lewis Research Center is discussed. The test set is a fully programmable, bit-error-rate (BER) test set designed for broadband modem-only and multichannel demultiplexer/demodulator characterization. It is currently configured for testing a multichannel demultiplexer/demodulator and was developed for the Advanced Research and Projects Agency under a Technology Reinvestment Program Cooperative Agreement entitled 'Millennium: 21st Century Broadband Digital Telecommunications Technology.' The test set can easily be modified to provide testing of other modems and multichannel demultiplexer/demodulator systems and is available to industry for such testing.

Ivancic, William D.↗

NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗