Water-landing Investigation of a Flat-bottom V-step Model and Comparison with a Theory Incorporating Planing Data
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Optimum proportional-plus-integral control settings for speed - fuel-flow control, determined by minimization of integral criteria, correlated well with analytically predicted optimum settings. Engine response data are given for a range of control settings around the optimum. An inherent nonlinearity in the speed-area loop necessitated the use of nonlinear controls. Response data for two such nonlinear control schemes are presented.
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The satellite laser ranging (SLR) technology experienced a large number of technical improvements since the early 1970's, leading now to a millimetric instrumental accuracy. Presently, it appears as useless to increase these instrumental performances as long as the atmospheric propagation delay suffers its actual imprecision. It has been proposed for many years to work in multiwavelength mode, but up to now the considerable technological difficulties of subpicosecond timing have seriously delayed such an approach. Then a new possibility is proposed, using a device which is not optimized now for SLR but has already given good results in the lower troposphere for wind measurement: the association of a radar and a sodar. While waiting for the 2-lambda methodology, this one could provide an atmospheric propagation delay at the millimeter level during a few years with only little technological investment.
Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.