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At least 811 records · Page 45

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NASA NTRS1984

Microprocessor control of photovoltaic systems

The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

Millner, A. R.↗

NASA NTRS1984

Computing in the presence of soft bit errors

It is shown that single-event-upsets (SEUs) due to cosmic rays are a significant source of single bit error in spacecraft computers. The physical mechanism of SEU, electron hole generation by means of Linear Energy Transfer (LET), it discussed with reference made to the results of a study of the environmental effects on computer systems of the Galileo spacecraft. Techniques for making software more tolerant of cosmic ray effects are considered, including: reducing the number of registers used by the software; continuity testing of variables; redundant execution of major procedures for error detection; and encoding state variables to detect single-bit changes. Attention is also given to design modifications which may reduce the cosmic ray exposure of on-board hardware. These modifications include: shielding components operating in LEO; removing low-power Schottky parts; and the use of CMOS diodes. The SEU parameters of different electronic components are listed in a table.

Rasmussen, R. D.↗

NASA NTRS1984

Development of a microprocessor controller for stand-alone photovoltaic power systems

A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

Millner, A. R.↗

NASA NTRS1986

Stanford Hardware Development Program

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

Peterson, A.↗

NASA NTRS1985

Pinhole array capacitor for oxide integrity analysis

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Buehler, M. G.↗

NASA NTRS1985

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗

NASA NTRS1985

JMOSFET: A MOSFET parameter extractor with geometry-dependent terms

The parameters from metal-oxide-silicon field-effect transistors (MOSFETs) that are included on the Combined Release and Radiation Effects Satellite (CRRES) test chips need to be extracted to have a simple but comprehensive method that can be used in wafer acceptance, and to have a method that is sufficiently accurate that it can be used in integrated circuits. A set of MOSFET parameter extraction procedures that are directly linked to the MOSFET model equations and that facilitate the use of simple, direct curve-fitting techniques are developed. In addition, the major physical effects that affect MOSFET operation in the linear and saturation regions of operation for devices fabricated in 1.2 to 3.0 mm CMOS technology are included. The fitting procedures were designed to establish single values for such parameters as threshold voltage and transconductance and to provide for slope matching between the linear and saturation regions of the MOSFET output current-voltage curves. Four different sizes of transistors that cover a rectangular-shaped region of the channel length-width plane are analyzed.

Buehler, M. G.↗

NASA NTRS1985

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated in this study, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗

NASA NTRS1985

Parameter extraction from spaceborne MOSFETs

An addressable matrix of 32 CMOS transistors was designed into a test chip to be flown on the Combined Release and Radiation Effects Satellite (CRRES). In this paper the matrix is described along with a SPICE-like parameter extraction procedure called JMOSFIT, and Cobalt 60 radiation test results are presented that illustrate the shift in the 21-MOSFET parameters derived from JMOSFIT.

Buehler, M. G.↗

NASA NTRS1986

Hardware requirements: A new generation partial reflection radar for studies of the equatorial mesosphere

A new partial reflection (PR) radar is being developed for operation at the proposed Equatorial Observatory. The system is being designed to make maximum use of recent advances in solid-state technology in order to minimize the power requirements. In particular, it is planned to use a solid-state transmitter in place of the tube transmitters previously used in PR systems. Solid-state transmitters have the advantages that they do not need high voltage supplies, they do not require cathode heaters with a corresponding saving in power consumption and parts are readily available and inexpensive. It should be possible to achieve 15 kW peak powers with recently announced fast switching transistors. Since high mean powers are desirable for obtaining good signal-to-noise ratios, it is also planned to phase code the transmitted pulses and decode after coherent integration. All decoding and signal processing will be carried out in dedicated microprocessors before the signals are passed to a microcomputer for on-line analysis. Recent tests have shown that an Olivetti M24 micro (an IBM compatible) running an 8-MHz clock with a 8087 coprocessor can analyze data at least as fast as the minicomputers presently being used with the Adelaide PR rad ar and at a significantly lower cost. The processed winds data will be stored in nonvolatile CMOS RAM modules; about 0.5 to 1 Mbyte is required to store one week's information.

Vincent, R. A.↗

NASA NTRS1986

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

Truong, T. K.↗

NASA NTRS1985

Solar powered hybrid sensor module program

Geo-orbital systems of the near future will require more sophisticated electronic and electromechanical monitoring and control systems than current satellite systems with an emphasis in the design on the electronic density and autonomy of the subsystem components. Results of a project to develop, design, and implement a proof-of-concept sensor system for space applications, with hybrids forming the active subsystem components are described. The design of the solar power hybrid sensor modules is discussed. Module construction and function are described. These modules combined low power CMOS electronics, GaAs solar cells, a crystal oscillatory standard UART data formatting, and a bidirectional optical data link into a single 1.25 x 1.25 x 0.25 inch hybrid package which has no need for electrical input or output. Several modules were built and tested. Applications of such a system for future space missions are also discussed.

Johnson, J. M.↗

NASA NTRS1985

SS focused technology: Gateways and NOS's

The extensions and enhancements of the fiber optic data bus technology supported by the Space Station Focused Technology Program are discussed. This includes the operating software for the network called the Network Operating System (NOS); gateways and bridges for multiple network topologies; and very large scale topology implimentations to shrink the size and power of the Bus Interface Unit (BIU) down to more manageable dimensions. CMOS is being investigated for the lower speed (parallel) logic. Gallium arsendide is being studied for the high speed (serial) logic.

Hartenstein, R.↗

NASA NTRS1985

Single event upset immune integrated circuits for Project Galileo

Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.

Giddings, A. E.↗

NASA NTRS1986

The Galileo single-event upset solution and risk assessment

The Galileo probe will be subject to radiation fields and energetic particle bombardment during its outward bound journey and in orbit around Jupiter and its moons. To avoid the occurrence and propagation of effects of single event upset (SEU) bit state changes induced by the bombardments attempts were made to harden the Galileo electronics against SEUs. The hazards are especially acute for Schottky diode and low-power Schottky TTL parts. The preventive action options which were scheduled are reviewed, noting the selection of CMOS chips as replacements for SEU-susceptible devices. The simulation and risk assessment that were performed to evaluate the potential success of the replacements are summarized, with emphasis on the data employed to ensure the accuracy of the assessments and the predicted effects of SEUs in the various Galileo subsystems.

Burdick, Garry M.↗

NASA NTRS1987

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

Shyu, H. C.↗

NASA NTRS1988

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.↗

NASA NTRS1988

Merging Digital Data With A Video Signal

Data displayed on television image of experiment. Video images of experiment sent with digital data on experiment to remote station. Digital data raw and unformatted or in form of characters. For minimal power consumption, interface circuit built of CMOS and HMOS integrated-circuit chips. Buffer/decoder circuit enables experiment computer to communicate with board without excessive loading of computer bus by board. Memory multiplexer/memory array implements buffer-swapping scheme as one buffer is read, other filled with new data.

Collins, Thomas J., III↗