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At least 811 records · Page 45

Launch Support Video Site

The goal of this project is to create a website that displays video, countdown clock, and event times to customers during launches, without needing to be connected to the internal operations network. The requirements of this project are to also minimize the delay in the clock and events to be less than two seconds. The two parts of this are the webpage, which will display the data and videos to the user, and a server to send clock and event data to the webpage. The webpage is written in HTML with CSS and JavaScript. The JavaScript is responsible for connecting to the server, receiving new clock data, and updating the webpage. JavaScript is used for this because it can send custom HTTP requests from the webpage, and provides the ability to update parts of the webpage without having to refresh the entire page. The server application will act as a relay between the operations network, and the open internet. On the operations network side, the application receives multicast packets that contain countdown clock and events data. It will then parse the data into current countdown times and events, and create a packet with that information that can be sent to webpages. The other part will accept HTTP requests from the webpage, and respond to them with current data. The server is written in C# with some C++ files used to define the structure of data packets. The videos for the webpage will be shown in an embedded player from UStream.

OFarrell, Zachary L.↗

A Trilateration Scheme for Relative Positioning

We introduce a trilateration scheme that evaluates the 3-dimensional (3-D) relative position between a reference spacecraft and a target spacecraft using raw-range measurements from a distance baseline of known locations, which we call “anchors”. The anchors can be antennas of a ground-based network (e.g., Deep Space Network (DSN) or Near Earth Network (NEN) stations), or satellites of a spacebased network (e.g., global positioning system (GPS) or tracking and data relay satellite (TDRS)). We define raw-range as the range that includes all the systematic errors that occur during range measurements. A unique feature of this approach is that accurate relative position is derived from a “differencing function” of raw-range measurements of the reference spacecraft and target spacecraft, thereby eliminating most of the systematic errors, such as media effects, ephemeris errors, instrument delays, clock bias, etc. There can be an arbitrary number of target spacecraft, and relative positioning of target spacecraft with respect to the reference spacecraft can be done simultaneously. In this paper, we first assume an idealized system in which clocks on the reference and target spacecraft are synchronized, with clocks of the anchors synchronized as well. We develop a novel iterative algorithm that computes the relative position of the target spacecraft with respect to the reference spacecraft. We illustrate the relative positioning method using the scenario of a network of three ground stations (i.e., the anchors) at Goldstone, California, USA, Madrid, Spain, and Marlargue, Argentina tracking two spacecraft at geosynchronous orbit distance. We demonstrate that the algorithm converges to submeter accuracy in estimating the relative position, in the presence of random errors and systematic errors in raw-range measurements, and in the presence of angular errors in estimating the pointing vectors between the anchors and the reference spacecraft. Next, we relax the requirement of perfect time synchronization between spacecraft, and show that by using an additional anchor, one can estimate and remove the clock biases between the reference and target spacecraft. We add a ground station at Kourou to the above example of three ground stations of Goldstone, Madrid, and Marlargue, and demonstrate that the updated algorithm also converges to meter-level accuracy (submeter in some cases) in the presence of clock biases in addition to the random errors, systematic errors, and angular errors as shown in the above case. We compare this scheme with a similar trilateration scheme for relative positioning scheme first proposed by Montenbruck in 2002.

Cheung, Kar-Ming↗

Advanced High-Speed 16-Bit Digitizer System

The fastest commercially available 16-bit ADC can only perform around 200 mega-samples per second (200 MS/s). Connecting ADC chips together in eight different time domains increases the quantity of samples taken by a factor of eight. This method of interleaving requires that the input signal being sampled is split into eight identical signals and arrives at each ADC chip at the same point in time. The splitting of the input signal is performed in the analog front end containing a wideband filter that impedance matches the input signal to the ADC chips. Each ADC uses a clock to tell it when to perform a conversion. Using eight unique clocks spaced in 45-degree increments is the method used to time shift when each ADC chip performs its conversion. Given that this control clock is a fixed frequency, the clock phase shifting is accomplished by tightly controlling the distance that the clock must travel, resulting in a time delay. The interleaved ADC chips will now generate digital data in eight different time domains. These data are processed inside a field-programmable gate array (FPGA) to move the data back into a single time domain and store it into memory. The FPGA also contains a Nios II processor that provides system control and data retrieval via Ethernet.

42 ENGINEERING↗

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

97 MATHEMATICS AND COMPUTING↗

Wire like link for cycle reproducible and cycle accurate hardware accelerator

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

97 MATHEMATICS AND COMPUTING↗

Low latency asynchronous interface circuits

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

42 ENGINEERING↗

Systems and methods for switched-inductor integrated voltage regulators

Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage using the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Methods and systems of synchronizer selection

A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

42 ENGINEERING↗

Discrete time analog front end circuit implemented in a receiver device

A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

42 ENGINEERING↗

Data exchange and processing synchronization in distributed systems

Systems, methods, techniques and apparatuses of asynchronous communication is distributed systems are disclosed. One exemplary embodiment is a method determining, with a plurality of agent nodes structured to communicate asynchronously in a distributed system, a first set of iterations including an iteration determined by each of the plurality of agent nodes; determining, with a first agent node of the plurality of agent nodes, a local vector clock; receiving, with the first agent node, a first iteration of the first set of iterations and a remote vector clock determined based on the first iteration; updating, with the first agent node, the local vector clock based on the received remote vector clock; and determining a first iteration of a second set of iterations based on the first set of iterations after determining all iterations of the first set of iterations have been received based on the local vector clock.

Cintuglu, Mehmet H.↗

Cross‐species complementation reveals conserved functions for EARLY FLOWERING 3 between monocots and dicots

Abstract Plant responses to the environment are shaped by external stimuli and internal signaling pathways. In both the model plant Arabidopsis thaliana ( Arabidopsis ) and crop species, circadian clock factors are critical for growth, flowering, and circadian rhythms. Outside of Arabidopsis, however, little is known about the molecular function of clock gene products. Therefore, we sought to compare the function of Brachypodium distachyon ( Brachypodium ) and Setaria viridis ( Setaria ) orthologs of EARLY FLOWERING 3, a key clock gene in Arabidopsis . To identify both cycling genes and putative ELF 3 functional orthologs in Setaria , a circadian RNA ‐seq dataset and online query tool (Diel Explorer) were generated to explore expression profiles of Setaria genes under circadian conditions. The function of ELF 3 orthologs from Arabidopsis, Brachypodium, and Setaria was tested for complementation of an elf3 mutation in Arabidopsis . We find that both monocot orthologs were capable of rescuing hypocotyl elongation, flowering time, and arrhythmic clock phenotypes. Using affinity purification and mass spectrometry, our data indicate that Bd ELF 3 and Sv ELF 3 could be integrated into similar complexes in vivo as At ELF 3. Thus, we find that, despite 180 million years of separation, Bd ELF 3 and Sv ELF 3 can functionally complement loss of ELF 3 at the molecular and physiological level.

59 BASIC BIOLOGICAL SCIENCES↗

F-state quenching with CH{sub 4} for buffer-gas cooled {sup 171}Y b{sup +} frequency standard

We report that methane, CH{sub 4}, can be used as an efficient F-state quenching gas for trapped ytterbium ions. The quenching rate coefficient is measured to be (2.8 ± 0.3) × 10{sup 6} s{sup −1} Torr{sup −1}. For applications that use microwave hyperfine transitions of the ground-state {sup 171}Y b ions, the CH{sub 4} induced frequency shift coefficient and the decoherence rate coefficient are measured as δν/ν = (−3.6 ± 0.1) × 10{sup −6} Torr{sup −1} and 1/T{sub 2} = (1.5 ± 0.2) × 10{sup 5} s{sup −1} Torr{sup −1}. In our buffer-gas cooled {sup 171}Y b{sup +} microwave clock system, we find that only ≤10{sup −8} Torr of CH{sub 4} is required under normal operating conditions to efficiently clear the F-state and maintain ≥85% of trapped ions in the ground state with insignificant pressure shift and collisional decoherence of the clock resonance.

74 ATOMIC AND MOLECULAR PHYSICS↗

Picosecond Synchronization System for the Distribution of Photon Pairs Through a Fiber Link Between Fermilab and Argonne National Laboratories

Here we demonstrate a three-node quantum network for C-band photon pairs using 2 pairs of 59 km of deployed fiber between Fermi and Argonne National Laboratories. The C-band pairs are directed to nodes using a standard telecommunication switch and the detection system is synchronized to picosecond scale timing resolution using a coexisting O-or L-band optical clock distribution system. We measure a reduction of coincidence to-accidental ratio (CAR) of the C-band pairs from 51 ± 2 to 5.3 ± 0.4 due to Raman scattering of the O-band clock pulses. Despite this reduction, the CAR is nevertheless suitable for quantum networks.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Closely spaced nanomagnets by dual e-beam exposure for low-energy nanomagnet logic

The effect of nanomagnet spacing on required clock field has been studied by micromagnetic simulation for supermalloy (Ni{sub 79}Fe{sub 16}Mo{sub 5}) dots with dimensions 90 Multiplication-Sign 60 Multiplication-Sign 20 nm{sup 3} and 120 Multiplication-Sign 60 Multiplication-Sign 20 nm{sup 3}. Reduction of the inter-magnet spacing for both dimensions has resulted in reduction of the required clock field in the simulation. A dual e-beam exposure technique has been developed to allow fabrication of ultra dense features using conventional poly(methylmethacrylate) e-beam resist. Nanomagnet logic (NML) datalines of supermalloy dots with {approx}10 nm and {approx}15 nm spacing have been fabricated using dual e-beam exposure with a 3{sigma} overlay accuracy of {approx}4 nm. Fabricated NML datalines have been characterized using magnetic force microscopy for various clock fields. Datalines of both spacing have shown proper NML functionality with a clock field as low as 60 mT.

36 MATERIALS SCIENCE↗

Nanosecond-level time synchronization of autonomous radio detector stations for extensive air showers

To exploit the full potential of radio measurements of cosmic-ray air showers at MHz frequencies, a detector timing synchronization within 1 ns is needed. Large distributed radio detector arrays such as the Auger Engineering Radio Array (AERA) rely on timing via the Global Positioning System (GPS) for the synchronization of individual detector station clocks. Unfortunately, GPS timing is expected to have an accuracy no better than about 5 ns. In practice, in particular in AERA, the GPS clocks exhibit drifts on the order of tens of ns. We developed a technique to correct for the GPS drifts, and an independent method used for cross-checks that indeed we reach nanosecond-scale timing accuracy by this correction. First, we operate a “beacon transmitter” which emits defined sine waves detected by AERA antennas recorded within the physics data. The relative phasing of these sine waves can be used to correct for GPS clock drifts. In addition to this, we observe radio pulses emitted by commercial airplanes, the position of which we determine in real time from Automatic Dependent Surveillance Broadcasts intercepted with a software-defined radio. From the known source location and the measured arrival times of the pulses we determine relative timing offsets between radio detector stations. We demonstrate with a combined analysis that the two methods give a consistent timing calibration with an accuracy of 2 ns or better. Consequently, the beacon method alone can be used in the future to continuously determine and correct for GPS clock drifts in each individual event measured by AERA.

47 OTHER INSTRUMENTATION↗

Ultrahigh-resolution spectroscopy with atomic or molecular dark resonances: Exact steady-state line shapes and asymptotic profiles in the adiabatic pulsed regime

Exact and asymptotic line shape expressions are derived from the semiclassical density matrix representation describing a set of closed three-level {Lambda} atomic or molecular states including decoherences, relaxation rates, and light shifts. An accurate analysis of the exact steady-state dark-resonance profile describing the Autler-Townes doublet, the electromagnetically induced transparency or coherent population trapping resonance, and the Fano-Feshbach line shape leads to the linewidth expression of the two-photon Raman transition and frequency shifts associated to the clock transition. From an adiabatic analysis of the dynamical optical Bloch equations in the weak field limit, a pumping time required to efficiently trap a large number of atoms into a coherent superposition of long-lived states is established. For a highly asymmetrical configuration with different decay channels, a strong two-photon resonance based on a lower states population inversion is established when the driving continuous-wave laser fields are greatly unbalanced. When time separated resonant two-photon pulses are applied in the adiabatic pulsed regime for atomic or molecular clock engineering, where the first pulse is long enough to reach a coherent steady-state preparation and the second pulse is very short to avoid repumping into a new dark state, dark-resonance fringes mixing continuous-wave line shape properties and coherent Ramsey oscillations are created. Those fringes allow interrogation schemes bypassing the power broadening effect. Frequency shifts affecting the central clock fringe computed from asymptotic profiles and related to the Raman decoherence process exhibit nonlinear shapes with the three-level observable used for quantum measurement. We point out that different observables experience different shifts on the lower-state clock transition.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Symmetry breaking in an extended O(2) model

Motivated by attempts to quantum simulate lattice models with continuous Abelian symmetries using discrete approximations, we study an extended-O(2) model in two dimensions that differs from the ordinary O(2) model by the addition of an explicit symmetry breaking term − h q cos ( q φ ) . Its coupling h q allows to smoothly interpolate between the O(2) model ( h q = 0 ) and a q -state clock model ( h q → ∞ ). In the latter case, a q -state clock model can also be defined for noninteger values of q . Thus, such a limit can also be considered as an analytic continuation of an ordinary q -state clock model to noninteger q . In previous work, we established the phase diagram for noninteger q in the infinite coupling limit ( h q → ∞ ). We showed that there is a second-order phase transition at low temperature and a crossover at high temperature. In this work, we seek to establish the phase diagram at finite values of the coupling using Monte Carlo and tensor methods. We show that for noninteger q , the second-order phase transition at low temperature and crossover at high temperature persist to finite coupling. For integer q = 2 , 3, 4, we know there is a second-order phase transition at infinite coupling (i.e. the well-known clock models). At finite coupling, we find that the critical exponents for q = 3 , 4 vary with the coupling, and for q = 4 the transition may turn into a Berezinskii-Kosterlitz-Thouless transition at small coupling. We comment on the similarities and differences of the phase diagrams with those of quantum simulators of the Abelian-Higgs model based on ladder-shaped arrays of Rydberg atoms. Published by the American Physical Society 2024

Astronomy & Astrophysics↗

Time evolution in quantum cosmology

A commonly adopted relational account of time evolution in generally covariant systems, and more specifically in quantum cosmology, is argued to be unsatisfactory, insofar as it describes evolution relative to observed readings of a clock that does not exist as a bona fide observable object. A modified strategy is proposed, in which evolution relative to the proper time that elapses along the worldline of a specific observer can be described through the introduction of a ''test clock,'' regarded as internal to, and hence unobservable by, that observer. This strategy is worked out in detail in the case of a homogeneous cosmology, in the context of both a conventional Schroedinger quantization scheme, and a 'polymer' quantization scheme of the kind inspired by loop quantum gravity. Particular attention is given to limitations placed on the observability of time evolution by the requirement that a test clock should contribute only a negligible energy to the Hamiltonian constraint. It is found that suitable compromises are available, in which the clock energy is reasonably small, while Dirac observables are reasonably sharply defined.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗