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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 793 records · Page 44
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

On-board fault-tolerant SAR processor for spaceborne imaging radar systems

A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.

imaging Radar↗
NASA NTRS2013

Onboard Radar Processor Development for Disaster Response

Natural hazards often result in significant loss of human lives, economic assets and productivity as well as significant damage to the ecosystem. Scientists have reported more frequent and intense natural disasters in recent years, which may well be attributed to climate change. Many of the disaster response efforts were hampered by lack of up-to-date knowledge of the state of the affected areas because damaged infrastructure rendered the areas inaccessible. Radar remote sensing is playing an increasingly critical role in providing timely information to disaster response agencies due to the increasing fidelity and availability of geospatial information products.

VV (vertical transmit and vertical receive)↗
NASA NTRS1997

High-Performance Software Emulation of 1750A Processor

We describe a software emulator of the MIL-STD-1750A architecture that executes 1750A code at a rate of about 4 MIPS on a Sun 200MHz Ultra2 work-station, and effectively several times faster than that when application-specific optimizations are used.

1750A↗
DOE OSTI2023

Sparse matrix‐vector and matrix‐multivector products for the truncated SVD on graphics processors

Summary Many practical algorithms for numerical rank computations implement an iterative procedure that involves repeated multiplications of a vector, or a collection of vectors, with both a sparse matrix and its transpose. Unfortunately, the realization of these sparse products on current high performance libraries often deliver much lower arithmetic throughput when the matrix involved in the product is transposed. In this work, we propose a hybrid sparse matrix layout, named CSRC, that combines the flexibility of some well‐known sparse formats to offer a number of appealing properties: (1) CSRC can be obtained at low cost from the popular CSR (compressed sparse row) format; (2) CSRC has similar storage requirements as CSR; and especially, (3) the implementation of the sparse product kernels delivers high performance for both the direct product and its transposed variant on modern graphics accelerators thanks to a significant reduction of atomic operations compared to a conventional implementation based on CSR. This solution thus renders considerably higher performance when integrated into an iterative algorithm for the truncated singular value decomposition (SVD), such as the randomized SVD or, as demonstrated in the experimental results, the block Golub–Kahan–Lanczos algorithm.

Aliaga, José I.↗
DOE OSTI2025

ReSpike: A Co-Design Framework for Evaluating SNNs on ReRAM-Based Neuromorphic Processors

With Moore’s law approaching its end, traditional von Neumann architectures are struggling to keep up with the exceeding performance and memory requirements of artificial intelligence and machine learning algorithms. Unconventional computing approaches such as neuromorphic computing that leverage spiking neural networks (SNNs) to perform computation are gaining traction and seek the paradigm shift necessary to sustain the increasing demands of modern applications. Novel memory technologies, such as resistive RAM (ReRAM), employ a crossbar architecture that possesses the inherent capability of efficiently computing vector-matrix multiplication—a dominant operation in SNNs. The prospect of naturally mapping SNNs to the crossbar structures provides a unique opportunity for achieving a high-performance, power-efficient neuromorphic system. In this work, we present ReSpike, which is a new framework, behavioral simulator, and architectural design based on ReRAM crossbar architectures, enabling modeling and co-design to achieve efficient execution of SNNs. We drive this co-design forward by quantifying the impact that ReRAM cell nonidealities have on the corresponding accuracy of an SNN application.

Asifuzzaman, Kazi [ORNL] (ORCID:0000000240044791)↗
DOE OSTI2024

Empowering a qudit-based quantum processor by traversing the dual bosonic ladder

Abstract High-dimensional quantum information processing has emerged as a promising avenue to transcend hardware limitations and advance the frontiers of quantum technologies. Harnessing the untapped potential of the so-called qudits necessitates the development of quantum protocols beyond the established qubit methodologies. Here, we present a robust, hardware-efficient, and scalable approach for operating multidimensional solid-state systems using Raman-assisted two-photon interactions. We then utilize them to construct extensible multi-qubit operations, realize highly entangled multidimensional states including atomic squeezed states and Schrödinger cat states, and implement programmable entanglement distribution along a qudit array. Our work illuminates the quantum electrodynamics of strongly driven multi-qudit systems and provides the experimental foundation for the future development of high-dimensional quantum applications such as quantum sensing and fault-tolerant quantum computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

A phononic interface between a superconducting quantum processor and quantum networked spin memories

We introduce a method for high-fidelity quantum state transduction between a superconducting microwave qubit and the ground state spin system of a solid-state artificial atom, mediated via an acoustic bus connected by piezoelectric transducers. Applied to present-day experimental parameters for superconducting circuit qubits and diamond silicon-vacancy centers in an optimized phononic cavity, we estimate quantum state transduction with fidelity exceeding 99% at a MHz-scale bandwidth. By combining the complementary strengths of superconducting circuit quantum computing and artificial atoms, the hybrid architecture provides high-fidelity qubit gates with long-lived quantum memory, high-fidelity measurement, large qubit number, reconfigurable qubit connectivity, and high-fidelity state and gate teleportation through optical quantum networks.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Certified randomness using a trapped-ion quantum processor

Although quantum computers can perform a wide range of practically important tasks beyond the abilities of classical computers, realizing this potential remains a challenge. An example is to use an untrusted remote device to generate random bits that can be certified to contain a certain amount of entropy. Certified randomness has many applications but is impossible to achieve solely by classical computation. Here we demonstrate the generation of certifiably random bits using the 56-qubit Quantinuum H2-1 trapped-ion quantum computer accessed over the Internet. Our protocol leverages the classical hardness of recent random circuit sampling demonstrations: a client generates quantum ‘challenge’ circuits using a small randomness seed, sends them to an untrusted quantum server to execute and verifies the results of the server. We analyse the security of our protocol against a restricted class of realistic near-term adversaries. Using classical verification with measured combined sustained performance of 1.1 × 10 18 floating-point operations per second across multiple supercomputers, we certify 71,313 bits of entropy under this restricted adversary and additional assumptions. Our results demonstrate a step towards the practical applicability of present-day quantum computers.

computer science↗
DOE OSTI2025

Topological prethermal strong zero modes on superconducting processors

Abstract Symmetry-protected topological phases 1–4 cannot be described by any local order parameter and are beyond the conventional symmetry-breaking model 5 . They are characterized by topological boundary modes that remain stable under symmetry respecting perturbations 1–4,6–8 . In clean, gapped systems without disorder, the stability of these edge modes is restricted to the zero-temperature manifold; at finite temperatures, interactions with mobile thermal excitations lead to their decay 9–11 . Here we report the observation of a distinct type of topological edge mode 12–14 , which is protected by emergent symmetries and persists across the entire spectrum, in an array of 100 programmable superconducting qubits. Through digital quantum simulation of a one-dimensional disorder-free stabilizer Hamiltonian, we observe robust long-lived topological edge modes over up to 30 cycles for a wide range of initial states. We show that the interaction between these edge modes and bulk excitations can be suppressed by dimerizing the stabilizer strength, leading to an emergent U(1) × U(1) symmetry in the prethermal regime of the system. Furthermore, we exploit these topological edge modes as logical qubits and prepare a logical Bell state, which exhibits persistent coherence, despite the system being disorder-free and at finite temperature. Our results establish a viable digital simulation approach 15–18 to experimentally study topological matter at finite temperature and demonstrate a potential route to construct long-lived, robust boundary qubits in disorder-free systems.

Science & Technology - Other Topics↗