Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “memory”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 793 records · Page 44
All sourcesNASA NTRSDOE OSTI
DOE OSTI2017

Distributed memory parallel Markov random fields using graph partitioning

Markov random fields (MRF) based algorithms have attracted a large amount of interest in image analysis due to their ability to exploit contextual information about data. Image data generated by experimental facilities, though, continues to grow larger and more complex, making it more difficult to analyze in a reasonable amount of time. Applying image processing algorithms to large datasets requires alternative approaches to circumvent performance problems. Aiming to provide scientists with a new tool to recover valuable information from such datasets, we developed a general purpose distributed memory parallel MRF-based image analysis framework (MPI-PMRF). MPI-PMRF overcomes performance and memory limitations by distributing data and computations across processors. The proposed approach was successfully tested with synthetic and experimental datasets. Additionally, the performance of the MPI-PMRF framework is analyzed through a detailed scalability study. We show that a performance increase is obtained while maintaining an accuracy of the segmentation results higher than 98%. The contributions of this paper are: (a) development of a distributed memory MRF framework; (b) measurement of the performance increase of the proposed approach; (c) verification of segmentation accuracy in both synthetic and experimental, real-world datasets

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Checksumming strategies for data in volatile memories

The increase in the number of processors needed to build exascale systems implies that the mean time between failure will further decrease, making it increasingly important to develop scalable techniques for fault tolerance. In this paper we develop an efficient checksum-based approach to fault tolerance for data in volatile memory systems, i.e., an approach without the need to save any data on stable persistent storage. The developed scheme is applicable in multiple scenarios, including: 1) online recovery of large read-only data structures from the memory of failed nodes, with very low storage overhead 2) online recovery from soft errors in blocked data, and 3) online recovery of read/write data via in-memory check-pointing. The approach uses a logical multi-dimension view of the data to be protected. Changing the dimensionality of the data view enables a trade-off between multiple factors, including the storage overheads, the checksum generation time, the failure recovery time, and the number of faults that can be tolerated. Experimental results demonstrating effectiveness are presented on a Cray XE6 system.

Arafat, Md H.↗
DOE OSTI2024

Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET

Here, in this work, we present a variation-tolerant and energy-efficient charge-domain Ferroelectric FET (FeFET) based Compute-in-Memory (CiM) array design that is compatible with both binary and multi-level cell memory sensing. We demonstrate that: 1) by exploiting FeFET as a nonvolatile switch, its high ON/OFF ratio in the subthreshold region can suppress the error introduced by the inaccurate ON state conductance, thus realizing robust CiM operations, unlike the current-domain CiM design where the computation results is highly sensitive to the device conductance variation; 2) by leveraging a dense dynamic random access memory (DRAM)-like 1FeFET1C cell structure, the proposed design benefits from the existing high density DRAM establishment while also significantly relaxing the capacitor retention and transistor leakage requirement; 3) the charge-domain CiM supports both binary FeFET with minimum overhead and MLC FeFET with tolerable latency for MLC state sensing, whose efficacy is validated experimentally on both cell-level and array-level; 4) the proposed CiM shows much better device variation resilience than conventional current-domain CiM, and also improves inference accuracy. Macro-level evaluation results demonstrate significantly higher energy efficiency and area efficiency compared to prior CiM works.

Duan, Jiahui [University of Notre Dame, IN (United↗
DOE OSTI2024

First Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and its Scalability for High-Density 3D Ferroelectric Capacitor Memory

In this article, we perform a comprehensive experimental and modeling study into the scaling of vertical 2T-nC ferroelectric random-access memory (FeRAM) hybrid cell to demonstrate a high performance and high-density 3D capacitor memory. We demonstrate: i) first time successful integration of the vertical 2T-3C FeRAM cell by stacking the vertical metal-ferroelectricmetal (MFM) stack on top of Si CMOS transistors; ii) successful experimental operation of the memory cell, including the quasi-nondestructive read out (QNRO) of the polarization without write back after 106 read cycles; iii) the write bit line (WBL) heavily screens the coupling between neighboring strings, making it a minor concern; V ) aggressive stacking of the WBLs, i.e., number of MFMs in a string, could facilitate the self-boosting during write operation due to ferroelectric linear capacitance (CFE), which allows self-boosted inhibition for Vw/2 scheme and worsens the Vw/3 scheme as disturb increases to intolerable 2Vw/3; v) aggressive horizontal scaling significantly increases the read disturb to cells on neighboring planes due to capacitance between two WBLs (Cz).

42 ENGINEERING↗
DOE OSTI2022

Evaluating Unified Memory Performance in HIP

Heterogeneous unified memory management between a CPU and a GPU is a major challenge in GPU computing. Recently, unified memory (UM) has been supported by software and hardware components on AMD computing platforms. The support could simplify the complexities of memory management. In this paper, we attempt to have a better understanding of UM by evaluating the performance of UM programs on an AMD MI100 GPU. More specifically, we evaluate data migration using UM against other data transfer techniques for the overall performance of an application, assess the impacts of three commonly used optimization techniques on the kernel execution time of a vector add sample, and compare the performance and productivity of selected benchmarks with and without UM. The performance overhead associated with UM is not trivial, but it can improve programming productivity by reducing lines of code for scientific applications. We aim to present early results and feedback on the UM performance to the vendor.

Jin, Zheming↗
DOE OSTI2019

Threshold Switching and Memory Behaviors of Epitaxially Regrown GaN-on-GaN Vertical $p-n$ Diodes With High Temperature Stability

This letter reports the observation of threshold switching and memory behaviors of epitaxially regrown GaN-on-GaN vertical p-n diodes. This mechanism was ascribed to the conductive path formed by traps in the insulating layer at the regrowth interface after soft breakdown. The device can reliably switch more than 1000 cycles at both room temperature and 300 °C with small fluctuation on the set and reset voltage. The set voltage increased with the increasing temperature due to the enhanced thermal detrapping effect that made it harder to form conductive path at high temperatures. Besides, the device showed memory behaviors when the reset voltage was higher than 4.4 V. This letter can serve as an important reference to further developing GaN-based memory devices and integrated circuits.

36 MATERIALS SCIENCE↗
DOE OSTI2026

MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator

We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation

This work presents a novel approach to configure 2T-nC ferroelectric RAM (FeRAM) for performing single cell logic-in-memory operations, highlighting its advantages in energy-efficient computation over conventional DRAM-based approaches. Unlike conventional 1T-1C dynamic RAM (DRAM), which incurs refresh overhead, 2T-nC FeRAM offers a promising alternative as a non-volatile memory solution with low energy consumption. Our key findings include the potential of quasi-nondestructive readout (QNRO) sensing in 2T-nC FeRAM for logic-in-memory (LiM) applications, demonstrating its inherent capability to perform inverting logic without requiring external modifications, a feature absent in traditional 1T-1C DRAM. We successfully implement the MINORITY function within a single cell of 2T-nC FeRAM, enabling universal NAND and NOR logic, validated through SPICE simulations and experimental data. Additionally, the research investigates the feasibility of 3D integration with 2T-nC FeRAM, showing substantial improvements in storage and computational density, facilitating bulk-bitwise computation. Our evaluation of eight real-world, data-intensive applications reveals that 2T-nC FeRAM achieves 2× higher performance and 2.5× lower energy consumption compared to DRAM. Furthermore, the thermal stability of stacked 2T-nC FeRAM is validated, confirming its reliable operation when integrated on a compute die. These findings emphasize the advantages of 2T-nC FeRAM for LiM, offering superior performance and energy efficiency over conventional DRAM.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Superconducting Hyperdimensional Associative Memory Circuit for Scalable Machine Learning

Here we propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of ~ 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Radiation-Induced Error Mitigation by Read-Retry Technique for MLC 3-D NAND Flash Memory

Here, we have evaluated the Read-Retry (RR) functionality of the 3-D NAND chip of multilevel-cell (MLC) configuration after total ionization dose (TID) exposure. The RR function is typically offered in the high-density state-of-the-art NAND memory chips to recover data once the default memory read method fails to correct data with error correction codes (ECCs). In this work, we have applied the RR method on the irradiated 3-D NAND chip that was exposed with a Co-60 gamma-ray source for TID up to 50 krad (Si). Based on our experimental evaluation results, we have proposed an algorithm to efficiently implement the RR method to extend the radiation tolerance of the NAND memory chip. Our experimental evaluation shows that the RR method coupled with ECC can ensure data integrity of MLC 3-D NAND for TID up to 50 krad (Si).

3-D NAND↗
DOE OSTI2021

Analytical Bit-Error Model of NAND Flash Memories for Dosimetry Application

In this work, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values (~ 20 krad(Si)) from measured data at lower TID values (<1 krad(Si)). Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin and the intrinsic errors on the dosimeter design using detailed experimentation.

3-D NAND↗
DOE OSTI2026

Memory-Aware External Facelist Calculation: A Data-Parallel Atomic Hash Counting Approach

Unstructured volumetric meshes serve as fundamental data representations in various scientific simulations and analyses. They play a crucial role in representing complex computational domains and are essential for important numerical techniques, such as finite element analysis. Whenever such a mesh is read from a file, streamed in-situ, or generated by algorithms, scientific visualization libraries rely on calculating the external surface of a geometry, named “external facelist”, to produce a polygonal mesh for rendering. Consequently, external facelist calculation has become one of the most widely used algorithms in the scientific visualization domain, necessitating optimal performance. In this paper, we explore relevant work on external facelist calculation algorithms in two common visualization libraries, VTK and Viskores, assess their performance and memory constraints, and introduce a novel memory-aware external facelist calculation algorithm employing an atomic hash counting approach. This algorithm fully leverages Viskores' data-parallel primitive operations, facilitating its execution across diverse many-core architectures. Our algorithm features the lowest memory footprint on the GPU and the second-lowest on the CPU among all evaluated methods, and it also delivers the fastest performance on both CPU and GPU. It has been made available under an open-source license in the VTK and Viskores visualization systems.

Tsalikis, Spiros [Kitware] (ORCID:0000000151137195↗
DOE OSTI2014

Quantifying ecological memory in plant and ecosystem processes

Abstract The role of time in ecology has a long history of investigation, but ecologists have largely restricted their attention to the influence of concurrent abiotic conditions on rates and magnitudes of important ecological processes. Recently, however, ecologists have improved their understanding of ecological processes by explicitly considering the effects of antecedent conditions. To broadly help in studying the role of time, we evaluate the length, temporal pattern, and strength of memory with respect to the influence of antecedent conditions on current ecological dynamics. We developed the stochastic antecedent modelling ( SAM ) framework as a flexible analytic approach for evaluating exogenous and endogenous process components of memory in a system of interest. We designed SAM to be useful in revealing novel insights promoting further study, illustrated in four examples with different degrees of complexity and varying time scales: stomatal conductance, soil respiration, ecosystem productivity, and tree growth. Models with antecedent effects explained an additional 18–28% of response variation compared to models without antecedent effects. Moreover, SAM also enabled identification of potential mechanisms that underlie components of memory, thus revealing temporal properties that are not apparent from traditional treatments of ecological time‐series data and facilitating new hypothesis generation and additional research.

Ogle, Kiona↗
DOE OSTI2016

A Limited-Memory Multiple Shooting Method for Weakly Constrained Variational Data Assimilation

Maximum-likelihood-based state estimation for dynamical systems with model error raises computational challenges in memory usage due to the much larger number of free variables when compared to the perfect model case. To address this challenge, we present a limited-memory method for maximum-likelihood-based estimation of state space models. We reduce the memory storage requirements by expressing the optimal states as a function of checkpoints bounding a shooting interval. All states can then be recomputed as needed from a recursion stemming from the optimality conditions. The matching of states at checkpoints is imposed, in a multiple shooting fashion, as constraints on the optimization problem, which is solved with an augmented Lagrangian method. We prove that for nonlinear systems under certain assumptions the condition number of the Hessian matrix of the augmented Lagrangian function is bounded above with respect to the number of shooting intervals. Hence the method is stable for increasing time horizon. The assumptions include satisfying the observability conditions of the linearized system on a shooting interval. We also propose a recursion-based gradient evaluation algorithm for computing the gradient, which in turn allows the algorithm to proceed by storing at any time only the checkpoints and the states on a shooting interval. We demonstrate our findings with simulations in different regimes for Burgers' equation.

Xu, Wanting↗
DOE OSTI2020

Low-Memory, Discrete Ordinates, Discontinuous Galerkin Methods for Radiative Transport

The discrete ordinates discontinuous Galerkin (SN-DG) method is a well-established and practical approach for solving the radiative transport equation. In this paper, we study a low-memory variation of the upwind SN-DG method. The proposed method uses a smaller finite element space that is constructed by coupling spatial unknowns across collocation angles, thereby yielding an approximation with fewer degrees of freedom than the standard method. Like the original SN-DG method, the low-memory variation still preserves the asymptotic diffusion limit and maintains the characteristic structure needed for mesh sweeping algorithms. While we observe second-order convergence in the scattering dominated, diffusive regime, the low-memory method is in general only first-order accurate. To address this issue, we use upwind reconstruction to recover second-order accuracy. Finally, for both methods, numerical procedures based on upwind sweeps are proposed to reduce the system dimension in the underlying Krylov solver strategy.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Trace-Driven Memory Access Pattern Recognition in Computational Kernels. In: WOSC '14 Proceedings of the Second Workshop on Optimizing Stencil Computations

Classifying memory access patterns is paramount to the selection of the right set of optimizations and determination of the parallelization strategy. Static analyses suffer from ambiguities present in source code, which modern compilation techniques, such as profile-guided optimization, alleviate by observing runtime behavior and feeding back into the compilation flow. This paper discusses a dynamic analysis technique for recognizing memory access patterns, with application to the stencils domain, and presents our design and C++ implementation using the memory-tracing tool Gleipnir. Finally, we evaluate and discuss the performance and matching capability of our classifiers in the context of the Polybench scientific benchmark suite, which includes both stencil and matrix computations.

Park, Eunjung↗
DOE OSTI2015

Memory Errors in Modern Systems: The Good, The Bad, and The Ugly

Several recent publications have shown that hardware faults in the memory subsystem are commonplace. These faults are predicted to become more frequent in future systems that contain orders of magnitude more DRAM and SRAM than found in current memory subsystems. These memory subsystems will need to provide resilience techniques to tolerate these faults when deployed in high-performance computing systems and data centers containing tens of thousands of nodes. Therefore, it is critical to understand the efficacy of current hardware resilience techniques to determine whether they will be suitable for future systems. In this paper, we present a study of DRAM and SRAM faults and errors from the field. We use data from two leadership-class high-performance computer systems to analyze the reliability impact of hardware resilience schemes that are deployed in current systems. Our study has several key findings about the efficacy of many currently deployed reliability techniques such as DRAM ECC, DDR address/command parity, and SRAM ECC and parity. We also perform a methodological study, and find that counting errors instead of faults, a common practice among researchers and data center operators, can lead to incorrect conclusions about system reliability. Lastly, we use our data to project the needs of future large-scale systems. We find that SRAM faults are unlikely to pose a significantly larger reliability threat in the future, while DRAM faults will be a major concern and stronger DRAM resilience schemes will be needed to maintain acceptable failure rates similar to those found on today's systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Newly Released Capabilities in the Distributed-Memory SuperLU Sparse Direct Solver

We present the new features available in the recent release of SuperLU_DIST, Version 8.1.1. SuperLU_DIST is a distributed-memory parallel sparse direct solver. The new features include (1) a 3D communication-avoiding algorithm framework that trades off inter-process communication for selective memory duplication, (2) multi-GPU support for both NVIDIA GPUs and AMD GPUs, and (3) mixed-precision routines that perform single-precision LU factorization and double-precision iterative refinement. Apart from the algorithm improvements, we also modernized the software build system to use CMake and Spack package installation tools to simplify the installation procedure. Throughout the article, we describe in detail the pertinent performance-sensitive parameters associated with each new algorithmic feature, show how they are exposed to the users, and give general guidance of how to set these parameters. We illustrate that the solver’s performance both in time and memory can be greatly improved after systematic tuning of the parameters, depending on the input sparse matrix and underlying hardware.

97 MATHEMATICS AND COMPUTING↗