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At least 793 records · Page 44

All sources NASA NTRS DOE OSTI

NASA NTRS1980

Application of software technology to a future spacecraft computer design

A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

Labaugh, R. J.↗

NASA NTRS1989

Optical detectors for GaAs MMIC integration: Technology assessment

Fiber optic links are being considered to transmit digital and analog signals in phased array antenna feed networks in space communications systems. The radiating elements in these arrays will be GaAs monolithic microwave integrated circuits (MMIC's) in numbers ranging from a few hundred to several thousand. If such optical interconnects are to be practical it appears essential that the associated components, including detectors, be monolithically integrated on the same chip as the microwave circuitry. The general issue of monolithic integration of microwave and optoelectronic components is addressed from the point of view of fabrication technology and compatibility. Particular attention is given to the fabrication technology of various types of GaAs optical detectors that are designed to operate at a wavelength of 830 nm.

Claspy, P. C.↗

NASA NTRS1989

Optical detectors for GaAs MMIC integration - Technology assessment

Claspy, P. C.↗

NASA NTRS1991

Ka-band MMIC microstrip array for high rate communications

In a recent technology assessment of alternative communication systems for the space exploration initiative (SEI), Ka-band (18 to 40 GHz) communication technology was identified to meet the mission requirements of telecommunication, navigation, and information management. Compared to the lower frequency bands, Ka-band antennas offer higher gain and broader bandwidths; thus, they are more suitable for high data rate communications. Over the years, NASA has played an important role in monolithic microwave integrated circuit (MMIC) phased array technology development, and currently, has an ongoing contract with Texas Instrument (TI) to develop a modular Ka-band MMIC microstrip subarray (NAS3-25718). The TI contract emphasizes MMIC integration technology development and stipulates using existing MMIC devices to minimize the array development cost. The objective of this paper is to present array component technologies and integration techniques used to construct the subarray modules.

Lee, R. Q.↗

NASA NTRS1991

Ka-band MMIC microstrip array for high rate communications

Lee, R. Q.↗

NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗

NASA NTRS2010

Update on Waveguide-Embedded Differential MMIC Amplifiers

There is an update on the subject matter of Differential InP HEMT MMIC Amplifiers Embedded in Waveguides (NPO-42857) NASA Tech Briefs, Vol. 33, No. 9 (September 2009), page 35. To recapitulate: Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The MMICs are designed integrally with, and embedded in, waveguide packages. The instant work does not mention InP HEMTs but otherwise reiterates part of the subject matter of the cited prior article, with emphasis on the following salient points: An MMIC is mounted in the electric-field plane ("E-plane") of a waveguide and includes a finline transition to each differential-amplifier stage. The differential configuration creates a virtual ground within each pair of transistor-gate fingers, eliminating the need for external radio-frequency grounding. This work concludes by describing a single-stage differential submillimeter-wave amplifier packaged in a rectangular waveguide and summarizing results of tests of this amplifier at frequencies of 220 and 305 GHz.

Kangaslahti, Pekka↗

NASA NTRS2009

Waveguide Transition for Submillimeter-Wave MMICs

An integrated waveguide-to-MMIC (monolithic microwave integrated circuit) chip operating in the 300-GHz range is designed to operate well on high-permittivity semiconductor substrates typical for an MMIC amplifier, and allows a wider MMIC substrate to be used, enabling integration with larger MMICs (power amplifiers). The waveguide-to- CBCPW (conductor-backed coplanar waveguide) transition topology is based on an integrated dipole placed in the E-plane of the waveguide module. It demonstrates low loss and good impedance matching. Measurement and simulation demonstrate that the loss of the transition and waveguide loss is less than 1-dB over a 340-to-380-GHz bandwidth. A transition is inserted along the propagation direction of the waveguide. This transition uses a planar dipole aligned with the maximum E-field of the TE10 waveguide mode as an inter face between the waveguide and the MMIC. Mode conversion between the coplanar striplines (CPS) that feed the dipole and the CBCPW transmission line is accomplished using a simple air-bridge structure. The bottom side ground plane is truncated at the same reference as the top-side ground plane, leaving the end of the MMIC suspended in air.

Leong, Kevin M.↗

NASA NTRS1991

Interface Circuit For Printer Port

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

Tucker, Jerry H.↗

NASA NTRS2008

HEMT Amplifiers and Equipment for their On-Wafer Testing

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Fung, King man↗

NASA NTRS1995

Integrated Cryogenic Satellite Communications Cross-Link Receiver Experiment

An experiment has been devised which will validate, in space, a miniature, high-performance receiver. The receiver blends three complementary technologies; high temperature superconductivity (HTS), pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuits (MMIC), and a miniature pulse tube cryogenic cooler. Specifically, an HTS band pass filter, InP MMIC low noise amplifier, HTS-sapphire resonator stabilized local oscillator (LO), and a miniature pulse tube cooler will be integrated into a complete 20 GHz receiver downconverter. This cooled downconverter will be interfaced with customized signal processing electronics and integrated onto the space shuttle's 'HitchHiker' carrier. A pseudorandom data sequence will be transmitted to the receiver, which is in low Earth orbit (LEO), via the Advanced Communication Technology Satellite (ACTS) on a 20 GHz carrier. The modulation format is QPSK and the data rate is 2.048 Mbps. The bit error rate (BER) will be measured in situ. The receiver is also equipped with a radiometer mode so that experiment success is not totally contingent upon the BER measurement. In this mode, the receiver uses the Earth and deep space as a hot and cold calibration source, respectively. The experiment closely simulates an actual cross-link scenario. Since the receiver performance depends on channel conditions, its true characteristics would be masked in a terrestrial measurement by atmospheric absorption and background radiation. Furthermore, the receiver's performance depends on its physical temperature, which is a sensitive function of platform environment, thermal design, and cryocooler performance. This empirical data is important for building confidence in the technology.

Romanofsky, R. R.↗

NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

NASA NTRS2004

Silicon-Germanium Films Grown on Sapphire for Ka-Band Communications Applications

NASA's vision in the space communications area is to develop a broadband data network in which there is a high degree of interconnectivity among the various satellite systems, ground stations, and wired systems. To accomplish this goal, we will need complex electronic circuits integrating analog and digital data handling at the Ka-band (26 to 40 GHz). The purpose of this project is to show the feasibility of a new technology for Ka-band communications applications, namely silicon germanium (SiGe) on sapphire. This new technology will have several advantages in comparison to the existing silicon-substrate- based circuits. The main advantages are extremely low parasitic reactances that enable much higher quality active and passive components, better device isolation, higher radiation tolerance, and the integration of digital and analog circuitry on a single chip.

Alterovitz, Samuel A.↗

NASA NTRS1983

Monolithic lead salt-silicon focal plane development

This paper is a summary of work done in the development of monolithic lead salt-silicon infrared focal plane technology. The photoconductive detector materials, PbS and PbSe are chemically deposited onto premetallized silicon MOSFET integrated circuit wafers. A variety of structures based on an implanted PMOS process were fabricated and evaluated. Operational results of an eight-element PbS array multiplexed on-chip are presented along with radiometric measurements on other integrated PbS-silicon MOSFET structures. PbS imagery is shown using one element of a 20-element array integrated on-chip.

Barrett, J. R.↗

NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

NASA NTRS1998

Computational Modeling of Semiconductor Dynamics at Femtosecond Time Scales

The Interchange No. NCC2-5149 deals with the emerging technology of photonic (or optoelectronic) integrated circuits (PICs or OEICs). In PICs, optical and electronic components are grown together on the same chip. To build such devices and subsystems, one needs to model the entire chip. PICs are useful for building components for integrated optical transmitters, integrated optical receivers, optical data storage systems, optical interconnects, and optical computers. For example, the current commercial rate for optical data transmission is 2.5 gigabits per second, whereas the use of shorter pulses to improve optical transmission rates would yield an increase of 400 to 1000 times. The improved optical data transmitters would be used in telecommunications networks and computer local-area networks. Also, these components can be applied to activities in space, such as satellite to satellite communications, when the data transmissions are made at optical frequencies. The research project consisted of developing accurate computer modeling of electromagnetic wave propagation in semiconductors. Such modeling is necessary for the successful development of PICs. More specifically, these computer codes would enable the modeling of such devices, including their subsystems, such as semiconductor lasers and semiconductor amplifiers in which there is femtosecond pulse propagation. Presently, there are no computer codes that could provide this modeling. Current codes do not solve the full vector, nonlinear, Maxwell's equations, which are required for these short pulses and also current codes do not solve the semiconductor Bloch equations, which are required to accurately describe the material's interaction with femtosecond pulses. The research performed under NCC2-5149 solves the combined Maxwell's and Bloch's equations.

Agrawal, Govind P.↗