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At least 793 records · Page 44

Flywheel Electronics

Requirements of the flywheel electronic system are to accelerate the momentum wheel to a fixed maximum speed when solar energy is available and to maintain a constant voltage on the spacecraft bus under varying loads when solar energy is not available. Requirements, energy flow control, types of motors considered, type of electronic control, and efficiency considerations, are outlined.

Nola, F. J.↗

The 25 kW resonant dc/dc power converter

The feasibility of processing 25-kW of power with a single, transistorized, series resonant converter stage was demonstrated by the successful design, development, fabrication, and testing of such a device which employs four Westinghouse D7ST transistors in a full-bridge configuration and operates from a 250-to-350 Vdc input bus. The unit has an overall worst-case efficiency of 93.5% at its full rated output of 1000 V and 25 A dc. A solid-state dc input circuit breaker and output-transient-current limiters are included in and integrated into the design. Full circuit details of the converter are presented along with the test data.

Robson, R. R.↗

The Development of an Airborne Instrumentation Computer System for Flight Test

Instrumentation interfacing frequently requires the linking of intelligent systems together, as well as requiring the link itself to be intelligent. The airborne instrumentation computer system (AICS) was developed to address this requirement. Its small size, approximately 254 by 133 by 140 mm (10 by 51/4 by 51/2 in), standard bus, and modular board configuration give it the ability to solve instrumentation interfacing and computation problems without forcing a redesign of the entire unit. This system has been used on the F-15 aircraft digital electronic engine control (DEEC) and its follow on engine model derivative (EMD) project and in an OV-1C Mohawk aircraft stall speed warning system. The AICS is presently undergoing configuration for use on an F-104 pace aircraft and on the advanced fighter technology integration (AFTI) F-111 aircraft.

Voice synthesizer↗

Getting the current out

Progress of a photovoltaic (PV) device from a research concept to a competitive power-generation source requires an increasing concern with current collection. The initial metallization focus is usually on contact resistance, since a good ohmic contact is desirable for accurate device characterization measurements. As the device grows in size, sheet resistance losses become important and a metal grid is usually added to reduce the effective sheet resistance. Later, as size and conversion efficiency continue to increase, grid-line resistance and cell shadowing must be considered simultaneously, because grid-line resistance is inversely related to total grid-line area and cell shadowing is directly related. A PV cell grid design must consider the five power-loss phenomena mentioned above: sheet resistance, contact resistance, grid resistance, bus-bar resistance and cell shadowing. Although cost, reliability and usage are important factors in deciding upon the best metallization system, this paper will focus only upon grid-line design and substrate material problems for flat-plate solar arrays.

Burger, D. R.↗

An operating system for future aerospace vehicle computer systems

The requirements for future aerospace vehicle computer operating systems are examined in this paper. The computer architecture is assumed to be distributed with a local area network connecting the nodes. Each node is assumed to provide a specific functionality. The network provides for communication so that the overall tasks of the vehicle are accomplished. The O/S structure is based upon the concept of objects. The mechanisms for integrating node unique objects with node common objects in order to implement both the autonomy and the cooperation between nodes is developed. The requirements for time critical performance and reliability and recovery are discussed. Time critical performance impacts all parts of the distributed operating system; e.g., its structure, the functional design of its objects, the language structure, etc. Throughout the paper the tradeoffs - concurrency, language structure, object recovery, binding, file structure, communication protocol, programmer freedom, etc. - are considered to arrive at a feasible, maximum performance design. Reliability of the network system is considered. A parallel multipath bus structure is proposed for the control of delivery time for time critical messages. The architecture also supports immediate recovery for the time critical message system after a communication failure.

Foudriat, E. C.↗

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗

Excess science accommodation capabilities and excess performance capabilities assessment for Mars Geoscience and Climatology Orbiter: Extended study

The excess science accommodation and excess performance capabilities of a candidate spacecraft bus for the Mars Geoscience and Climatology Orbiter MGCO mission are assessed. The appendices are included to support the conclusions obtained during this contract extension. The appendices address the mission analysis, the attitude determination and control, the propulsion subsystem, and the spacecraft configuration.

Clark, K.↗

Spacecraft servicing demonstration plan

A preliminary spacecraft servicing demonstration plan is prepared which leads to a fully verified operational on-orbit servicing system based on the module exchange, refueling, and resupply technologies. The resulting system can be applied at the space station, in low Earth orbit with an orbital maneuvering vehicle (OMV), or be carried with an OMV to geosynchronous orbit by an orbital transfer vehicle. The three phase plan includes ground demonstrations, cargo bay demonstrations, and free flight verifications. The plan emphasizes the exchange of multimission modular spacecraft (MMS) modules which involves space repairable satellites. Three servicer mechanism configurations are the engineering test unit, a protoflight quality unit, and two fully operational units that have been qualified and documented for use in free flight verification activity. The plan balances costs and risks by overlapping study phases, utilizing existing equipment for ground demonstrations, maximizing use of existing MMS equipment, and rental of a spacecraft bus.

Bergonz, F. H.↗

The Development of an Airborne Instrumentation Computer System for Flight Test

Instrumentation interfacing frequently requires the linking of intelligent systems together, as well as requiring the link itself to be intelligent. The airborne instrumentation computer system (AICS) was developed to address this requirement. Its small size, approximately 254 by 133 by 140 mm (10 by 51/4 by 51/2 in), standard bus, and modular board configuration give it the ability to solve instrumentation interfacing and computation problems without forcing a redesign of the entire unit. This system has been used on the F-15 aircraft digital electronic engine control (DEEC) and its follow on engine model derivative (EMD) project and in an OV-1C Mohawk aircraft stall speed warning system. The AICS is presently undergoing configuration for use on an F-104 pace aircraft and on the advanced fighter technology integration (AFTI) F-111 aircraft.

Glenn A Bever↗

The ACTS Flight System - Cost-Effective Advanced Communications Technology

The multibeam communications package (MCP) for the Advanced Communications Technology Satellite (ACTS) to be STS-launched by NASA in 1988 for experimental demonstration of satellite-switched TDMA (at 220 Mbit/sec) and baseband-processor signal routing (at 110 or 27.5 Mbit/sec) is characterized. The developmental history of the ACTS, the program definition, and the spacecraft-bus and MCP parameters are reviewed and illustrated with drawings, block diagrams, and maps of the coverage plan. Advanced features of the MPC include 4.5-dB-noise-figure 30-GHz FET amplifiers and 20-GHz TWTA transmitters which provide either 40-W or 8-W RF output, depending on rain conditions. The technologies being tested in ACTS can give frequency-reuse factors as high as 20, thus greatly expanding the orbit/spectrum resources available for U.S. communications use.

Holmes, W. M., Jr.↗

Operational characteristics of the dispersed sensor processor mesh

The dispersed sensor processing mesh (DSPM) is part of an experimental system used to pursue a proof of concept for an advanced fault-tolerant communication strategy. The DSPM experiments incorporate sensors and effectors into an ultra-reliable nodal network in which a central bus controller performs algorithms to grow and maintain the network. The experiments demonstrate that DSPM is an achievable communication network that can sustain failures and continue to function properly. The results of the experiment give insights into the unique characteristics of the DSPM network and the network's capacity to limit physical damage propagation, limit damaged-data propagation, and to survive cyclic communication paths. This paper describes the concept, mechanization, and performance of the DSPM system in a real-time flight-critical environment.

Abbott, L. W.↗

Fault detection, isolation and reconfiguration in FTMP Methods and experimental results

The Fault-Tolerant Multiprocessor (FTMP) is a highly reliable computer designed to meet a goal of 10 to the -10th failures per hour and built with the objective of flying an active-control transport aircraft. Fault detection, identification, and recovery software is described, and experimental results obtained by injecting faults in the pin level in the FTMP are presented. Over 21,000 faults were injected in the CPU, memory, bus interface circuits, and error detection, masking, and error reporting circuits of one LRU of the multiprocessor. Detection, isolation, and reconfiguration times were recorded for each fault, and the results were found to agree well with earlier assumptions made in reliability modeling.

Lala, J. H.↗

The LSLE echocardiograph - Commercial hardware aboard Spacelab

The Life Sciences Laboratory Equipment Echocardiograph, a commercial 77020AC Ultrasound Imaging System modified to meet NASA's spacecraft standards, is described. The assembly consists of four models: display and control, scanner, scan converter, and physioamplifiers. Four separate processors communicate over an IEE-488 bus, and the system has more than 6000 individual components on 35 printed circuit cards. Three levels of self test are provided: a short test during power up, a basic test initiated by a front panel switch, and interactive tests for specific routines. Default mode operation further enhances reliability. Modifications of the original system include the replacement of ac power supplies with dc to dc converters, a slide-out keyboard (to prevent accidental operation), Teflon insulated wire, and additional shielding for the ultrasound transducer cable.

Schwarz, R.↗

Low-Voltage Protection For Volatile Computer Memories

Short-circuit current provides minimum memory power. Protective circuit includes dc-to-dc converter that supplies keep-alive voltage to memories when short circuit occurs in any of system loads. Converter powered by lowvoltage across two of three series diodes generated by short-circuit bus current. Relay switch is in open (short-circuit-detected) position. Protective circuit useful wherever necessary to improve reliability of volatile memories or other circuits that must not lose power.

Detwiler, R. C.↗

Experimental Parallel-Processing Computer

Master processor supervises slave processors, each with its own memory. Computer with parallel processing serves as inexpensive tool for experimentation with parallel mathematical algorithms. Speed enhancement obtained depends on both nature of problem and structure of algorithm used. In parallel-processing architecture, "bank select" and control signals determine which one, if any, of N slave processor memories accessible to master processor at any given moment. When so selected, slave memory operates as part of master computer memory. When not selected, slave memory operates independently of main memory. Slave processors communicate with each other via input/output bus.

Mcgregor, J. W.↗

Space America's commercial space program

Space America prepared a private sector land observing space system which includes a sensor system with eight spectral channels configured for stereoscopic data acquisition of four stereo pairs, a spacecraft bus with active three-axis stabilization, a ground station for data acquisition, preprocessing and retransmission. The land observing system is a component of Space America's end-to-end system for Earth resources management, monitoring and exploration. In the context of the Federal Government's program of commercialization of the US land remote sensing program, Space America's space system is characteristic of US industry's use of advanced technology and of commercial, entrepreneurial management. Well before the issuance of the Request for Proposals for Transfer of the United States Land Remote Sensing Program to the Private Sector by the US Department of Commerce, Space Services, Inc., the managing venturer of Space America, used private funds to develop and manage its sub-orbital launch of its Conestoga launch vehicle.

Macleod, N. H.↗

Parallel, iterative solution of sparse linear systems: Models and architectures

A model of a general class of asynchronous, iterative solution methods for linear systems is developed. In the model, the system is solved by creating several cooperating tasks that each compute a portion of the solution vector. A data transfer model predicting both the probability that data must be transferred between two tasks and the amount of data to be transferred is presented. This model is used to derive an execution time model for predicting parallel execution time and an optimal number of tasks given the dimension and sparsity of the coefficient matrix and the costs of computation, synchronization, and communication. The suitability of different parallel architectures for solving randomly sparse linear systems is discussed. Based on the complexity of task scheduling, one parallel architecture, based on a broadcast bus, is presented and analyzed.

Reed, D. A.↗