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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

HamLib: A Library of Hamiltonians for Benchmarking Quantum Algorithms and Hardware

For a considerable time, large datasets containing problem instances have proven valuable for analyzing computer hardware, software, and algorithms. One notable example of the value of large datasets is ImageNet [1], a vast repository of images that has been instrumental in testing numerous deep learning packages. Similarly, in the domain of computational chemistry and materials science, the availability of extensive datasets such as the Protein Data Bank [2], the Materials Project [3], and QM9 [4] has greatly facilitated the evaluation of new algorithms and software approaches, while also promoting standardization within the field. These well-defined datasets and problem instances, in turn, serve as the foundation for creating benchmarking suites like MLPerf [5] and LINPACK [6], [7]. These suites enable fair and rigorous comparisons of different methodologies and solutions, fostering continuous advancements in various areas of computer science and beyond.

Sawaya, Nicolas PD↗
DOE OSTI2023

Improving Signal-to-Noise Ratio (SNR) for Readout Signals Using Adaptive Filters on Reconfigurable Controls Hardware

This study investigates the optimization of Signal-to-Noise Ratio (SNR) in superconducting quantum computing readout signals through adaptive filtering. Quantum computing technology has the potential to revolutionize various fields by delivering exponential speedup in solving certain computational problems. However, the technology's practical implementation is hindered by the difficulty of extracting clean, reliable signals during the readout phase, with various sources of noise presenting a significant barrier to clean signals. This noise, often present in readout profiles due to imperfect isolation, degrades the system's overall SNR, thus impeding the ability to extract the quantum state accurately. The research leverages the power of adaptive filtering to improve the SNR of quantum computing readout signals. Specifically, an adaptive filter is implemented in a PYNQ overlay on an FPGA, and eventually will be connected to a quantum computing system. The system models the noise with a Least Mean Squares (LMS) adaptive filter, and then subtracts the estimated noise from the received signal to improve the SNR. A Direct Memory Access (DMA) channel is used to handle the signal processing, delivering efficient, high-speed data transfer between the PYNQ system and the hardware. The study explores the benefits of this adaptive filtering technique, potentially providing a significant contribution to practical and fast quantum computing.

Johnson, Hans↗
DOE OSTI2025

Visual Analytics of Crosstalk in Quantum Hardware

Crosstalk remains a major obstacle to building scalable and fault-tolerant quantum computers. Conventional diagnostic techniques-often based on numerical simulation or statistical modeling-struggle to scale with hardware complexity and offer limited interpretability. In this work, we present a visual analytics framework for diagnosing qubit crosstalk using lightweight, circuit-based models integrated with an interactive user interface. Our approach quantifies correlations between active and idle qubits under parameterized single- and twoqubit operations, enabling detection of both spatial and gateinduced crosstalk. The system incorporates qubit topology and gate performance data to support sector-based exploration and correlation mapping. This tool assists users in identifying correlated error sources, informing qubit placement strategies, and guiding noise-aware circuit design.

Chae, Junghoon [ORNL] (ORCID:0000000206016746)↗
DOE OSTI2018

Internet-of-Things Hardware-in-the-Loop Simulation Architecture for Providing Frequency Regulation With Demand Response

Following recent advances in network infrastructure, cloud computing, and embedded systems, fascinating work is underway exploring the utility of demand response in increasing grid stability while permitting high penetration of intermittent renewable distributed generation resources. Although works have demonstrated diverse theoretical advantages of demand response programs, little real-world data are available and utilities generally remain reticent in moving forward with large-scale implementation due to risks inherent to any modification of the power system. Deciding that the next pertinent step in bringing demand response from theory to technology is developing an Internet-of-things hardware-in-the-loop simulation power system integrated device capable of empirically testing the theoretical mechanisms, this work presents an architecture testbed for providing demand response (telemetric monitoring and actuation of loads), which is real node in a power system simulation where virtual node's parameters derive real node data. Finally, we test a demand response algorithm, which provides frequency regulation services.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Hardware Design of Medium Voltage SiC-Based Modular Multilevel Converters for Grid-Tied Applications

This paper presents a design of a 10 kV silicon carbide (SiC) MOSFET based modular multilevel converter (MMC). The MMC functions as the interconnection between a 24 kV dc bus and a 13. SkV distribution grid. This paper focuses on the hardware design of the MMC and its submodules. The gate driver, auxiliary power supply and bus bur in submodules are major components that need to meet high dv/dt immunity and high insulation voltage requirements. The gate driver achieves over 200 kV/us common mode transient immunity (CMTI). Its associated auxiliary power supply is based on an on-board transformer with over 30 kV insulation capability and 1.4 pF barrier capacitance. The busbar achieves less than 11 kV/cm electric field in the air to avoid partial discharges. Validation tests of the MMC submodule were performed by double pulse tests at 5 kV and buck converter tests at3 kV, 52A (peak). Reliable operations were achieved in validation tests.

auxiliary power supply↗
DOE OSTI2021

Hardware-in-the-Loop Investigation of Emissions Challenges in Hybrid Medium- and Heavy-Duty Powertrains Using a Pre-Production Diesel-Electric Parallel Hybrid System With and Without Stop-Start Operation

Hybrid electric powertrains are a growing market in medium- and heavy-duty applications. There is a lack of available information to understand the challenges in the integration of engine platforms into electrified powertrains, such as cold-start, restart, and load-reduction effects on emissions and emission control devices. Results from the Heavy Heavy-Duty Diesel Truck (HHDDT) cycle using a conventional medium-duty diesel engine were compared with those of a parallel hybrid architecture. Oak Ridge National Laboratory in collaboration with the US Department of Energy and Odyne Systems, LLC developed a powertrain in a hardware-in-the-loop environment, integrating the Odyne Systems, LLC medium-duty parallel hybrid system, which was used for the hybrid portion of this study. Experiments under the HHDDT cycle showed increasing improvements in fuel consumption and engine-out emissions with the integration of stop/start, hybrid, and hybrid with stop/start. However, the effects of load reduction and exhaust temperature on the thermal management strategy have shown an increase in fueling in the second part of the HHDDT cycle. Four configurations of medium-duty electrification were studied and contributed to building a unique data set containing combustion, emissions, and system integration data. Each electrification level was compared with the conventional baseline. The calibration of the conventional engine was not altered for this study. Opportunities to tailor the combustion process were identified with the stop/start strategy.

Lerin, Chloe↗
DOE OSTI2014

TU-F-18C-07: Hardware Advances for MTF Improvement in Dedicated Breast CT

Purpose: In this study, we have designed and implemented a prototype dedicated breast CT system (bCT) to improve the spatial resolution characteristics, in order to improve detection of micro-calcifications. Methods: A 10.8 kW water-cooled, tungsten anode x-ray tube, running up to 240 mA at 60 kV, coupled with an x-ray generator specifically designed for this application, and 0.3 mm of added copper filter was used to generate x-ray pulses. A CsI CMOS flat panel detector with a pixel pitch of 0.075 mm in native binning mode was used. The system geometry was designed in a way to achieve an FOV on par with similar bCT prototypes, resulting in a magnification factor of 1.39. A 0.013 mm tungsten wire was used to generate point spread functions. Multiple scans were performed with different numbers of projections, different reconstruction kernel sizes and different reconstruction filters to study the effects of each parameter on MTF. The resulting MTFs were then evaluated quantitatively using the generated PFSs. Duplicate scans with the same parameters were performed on two other dedicated breast CT systems to compare the performance of the new prototype. Results: The results of the MTF experiments demonstrate a significant improvement in the spatial resolution characteristics. In the new prototype, using the pulsed x-ray source results in a restoration of the azimuthal MTF degradation, due to motion blurring previously seen in other bCT systems. Moreover, employing the higher resolution x-ray detector considerably improves the MTF. The MTF at 10% of the new system is at 3.5 1/mm, a factor of 4.36 greater than an earlier bCT scanner. Conclusion: The MTF analysis of the new prototype bCT shows that using the new hardware and control results in a significant improvement in visualization of finer detail. This suggests that the visualization of micro-calcifications will be significantly improved.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2016

SU-C-202-07: Protocol and Hardware for Improved Flood Field Calibration of TrueBeam FFF Cine Imaging

Purpose: Flattening filter free photon energies are commonly used for high dose treatments such as SBRT, where localization accuracy is essential. Often, MV cine imaging may be employed to verify correct localization. TrueBeam Electronic Portal Imaging Devices (EPIDs) equipped with the 40×30cm{sup 2} Image Detection Unit (IDU) are prone to image saturation at the image center especially for higher dose rates. While saturation often does not occur for cine imaging during treatment because the beam is attenuated by the patient, the flood field calibration is affected when the standard calibration procedure is followed. Here we describe the hardware and protocol to achieve improved image quality for this model of TrueBeam EPID. Methods: A stainless steel filter of uniform thickness was designed to have sufficient attenuation to avoid panel saturation for both 6XFFF and 10XFFF at the maximum dose rates (1400 MU/min & 2400 MU/min, respectively). The cine imaging flood field calibration was then acquired with the filter in place for the FFF energies under the standard calibration geometry (SDD=150cm). Image quality during MV cine was assessed with & without the modified flood field calibration using a low contrast resolution phantom and an anthropomorphic phantom. Results: When the flood field is acquired using the standard procedure (no filter in place), a pixel gain artifact is clearly present in the image center (r=3cm for 10XFFF at 2400 MU/min) which appears similar to and may be mis-attributed to panel saturation in the subject image. The artifact obscured all low contrast inserts at the image center and was also visible on the anthropomorphic phantom. Using the filter for flood field calibration eliminated the artifact. Conclusion: Use of a modified flood field calibration procedure improves image quality for cine MV imaging with TrueBeams equipped with the 40×30cm{sup 2} IDU.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2016

SU-F-R-12: Prediction of TrueBeam Hardware Issues Using Trajectory Log Analysis

Purpose: To predict potential failures of hardware within the Varian TrueBeam linear accelerator in order to proactively replace parts and decrease machine downtime. Methods: Machine downtime is a problem for all radiation oncology departments and vendors. Most often it is the result of unexpected equipment failure, and increased due to lack of in-house clinical engineering support. Preventative maintenance attempts to assuage downtime, but often is ineffective at preemptively preventing many failure modes such as MLC motor failures, the need to tighten a gantry chain, or the replacement of a jaw motor, among other things. To attempt to alleviate downtime, software was developed in house that determines the maximum value of each axis enumerated in the Truebeam trajectory log files. After patient treatments, this data is stored in a SQL database. Microsoft Power BI is used to plot the average maximum error of each day of each machine as a function of time. The results are then correlated with actual faults that occurred at the machine with the help of Varian service engineers. Results: Over the course of six months, 76,312 trajectory logs have been written into the database and plotted in Power BI. Throughout the course of analysis MLC motors have been replaced on three machines due to the early warning of the trajectory log analysis. The service engineers have also been alerted to possible gantry issues on one occasion due to the aforementioned analysis. Conclusion: Analyzing the trajectory log data is a viable and effective early warning system for potential failures of the TrueBeam linear accelerator. With further analysis and tightening of the tolerance values used to determine a possible imminent failure, it should be possible to pinpoint future issues more thoroughly and for more axes of motion.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2017

New hardware and software platform for experiments on a HUBER-5042 X-ray diffractometer with a DISPLEX DE-202 helium cryostat in the temperature range of 20–300 K

Huber-5042 diffractometer with a closed-cycle Displex DE-202 helium cryostat is a unique scientific instrument for carrying out X-ray diffraction experiments when studying the single crystal structure in the temperature range of 20–300 K. To make the service life longer and develop new experimental techniques, the diffractometer control is transferred to a new hardware and software platform. To this end, a modern computer; a new detector reader unit; and new control interfaces for stepper motors, temperature controller, and cryostat vacuum pumping system are used. The system for cooling the X-ray tube, the high-voltage generator, and the helium compressor and pump for maintaining the desired vacuum in the cryostat are replaced. The system for controlling the primary beam shutter is upgraded. A biological shielding is installed. The new program tools, which use the Linux Ubuntu operating system and SPEC constructor, include a set of drivers for control units through the aforementioned interfaces. A program for searching reflections from a sample using fast continuous scanning and a priori information about crystal is written. Thus, the software package for carrying out the complete cycle of precise diffraction experiment (from determining the crystal unit cell to calculating the integral reflection intensities) is upgraded. High quality of the experimental data obtained on this equipment is confirmed in a number of studies in the temperature range from 20 to 300 K.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Hardware and software for ground tests of onboard charged particle spectrometers

The article presents a hardware and software complex for ground tests of onboard charged particle spectrometers that are designed at the National Research Nuclear University MEPhI for monitoring of nuclear-physical factors of space weather and can be installed in a wide class of satellites. The structural scheme and operating principles of component parts are discussed. The main algorithm and software features are presented. The technique of ground spectrometer tests and calibrations in various measurement modes at atmospheric cosmic particle flows, both in autonomous laboratories and in interface tests as part of a satellite, is also described.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Towards Batched Linear Solvers on Accelerated Hardware Platforms

As hardware evolves, an increasingly effective approach to develop energy efficient, high-performance solvers, is to design them to work on many small and independent problems. Indeed, many applications already need this functionality, especially for GPUs, which are known to be currently about four to five times more energy efficient than multicore CPUs for every floating-point operation. In this paper, we describe the development of the main one-sided factorizations: LU, QR, and Cholesky; that are needed for a set of small dense matrices to work in parallel. We refer to such algorithms as batched factorizations. Our approach is based on representing the algorithms as a sequence of batched BLAS routines for GPU-contained execution. Note that this is similar in functionality to the LAPACK and the hybrid MAGMA algorithms for large-matrix factorizations. But it is different from a straightforward approach, whereby each of GPU's symmetric multiprocessors factorizes a single problem at a time. We illustrate how our performance analysis together with the profiling and tracing tools guided the development of batched factorizations to achieve up to 2-fold speedup and 3-fold better energy efficiency compared to our highly optimized batched CPU implementations based on the MKL library on a two-sockets, Intel Sandy Bridge server. Compared to a batched LU factorization featured in the NVIDIA's CUBLAS library for GPUs, we achieves up to 2.5-fold speedup on the K40 GPU.

Haidar, Azzam↗
DOE OSTI2022

The SODA Approach: Leveraging High-Level Synthesis for Hardware/Software Co-design and Hardware Specialization: Invited

Novel "converged" applications combine phases of scientific simulation with data analysis and machine learning. Each computational phase can benefit from specialized accelerators. However, algorithms evolve so quickly that mapping them on existing accelerators is suboptimal or even impossible. This paper presents the SODA (Software Defined Accelerators) framework, a modular, multi-level, open-source, no-human-in-the-loop, hardware synthesizer that enables end-to-end generation of specialized accelerators. SODA is composed of SODA-Opt, a high-level frontend developed in MLIR that interfaces with domain-specific programming frameworks and allows performing system level design, and Bambu, a state-of-the-art high-level synthesis engine that can target different device technologies. The framework implements design space exploration as compiler optimization passes. We show how the modular, yet tight, integration of the high-level optimizer and lower-level HLS tools enables the generation of accelerators optimized for the computational patterns of converged applications. We then discuss some of the research opportunities that such a framework allows, including system-level design, profile driven optimization, and supporting new optimization metrics.

Bohm Agostini, Nicolas↗
DOE OSTI2022

An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration

The generation of custom hardware accelerators for applications implemented within high-level productive programming frameworks requires considerable manual effort. To automate this process, we introduce \sodaopt, a compiler tool that extends the MLIR infrastructure. \sodaopt automatically searches, outlines, tiles, and pre-optimizes relevant code regions to generate high-quality accelerators through high-level synthesis. \sodaopt can support any high-level programming framework and domain-specific language that interface with the MLIR infrastructure. By leveraging MLIR, \sodaopt solves compiler optimization problems with specialized abstractions. Backend synthesis tools connect to \sodaopt through progressive intermediate representation lowerings. \sodaopt interfaces to a design space exploration engine to identify the combination of compiler optimization passes and options that provides high-performance generated designs for different backends and targets. We demonstrate the practical applicability of the compilation flow by exploring the automatic generation of accelerators for deep neural networks operators outlined at arbitrary granularity and by combining outlining with tiling on large convolution layers. Experimental results with kernels from the PolyBench benchmark show that \sodaopt high-level optimizations improve execution delays of synthesized accelerators up to 60x. We also show that for the selected kernels, our solution outperforms the current of state-of-the art in more than 70% of the benchmarks and provides better average speedup in 55% of them.

Bohm Agostini, Nicolas↗
DOE OSTI2023

Software-Hardware Co-design of Heterogeneous SmartNIC System for Recommendation Models Inference and Training

Deep Learning Recommendation Models (DLRMs) are critical applications in various domains and have evolved as one of the single largest machine learning applications. Trillions of DLRM parameters exceed the on-chip memory capacity of GPUs. Large-scale multi-node systems are required for distributed DLRM inference and training, which suffer from the all-to-all communication bottleneck, mainly limiting the scalability of ever-growing DLRMs. In recent years, SmartNICs have evolved with coupled computation and communication capabilities providing opportunities for a powerful heterogeneous device in the system. However, there isn't such a distributed system that fully leverages the abundant smartNIC resources that resolve the scalability issue of DLRMs. In this work, we proposed a software-hardware co-design of a heterogeneous smartNIC system that resolves the communication bottleneck of distributed DLRMs, mitigates the memory bandwidth pressure, and improves computation efficiency. We provide a set of smartNIC designs of cache systems (including local cache and remote cache) and smartNIC computation kernels which reduce data movement, relieve memory lookup intensity, and improve the GPU's computation efficiency. In addition, we propose a graph algorithm that improves the data locality of queries within batches which optimizes the overall system performance with higher data reuse. Our evaluation shows that our system achieves 2.1x latency speedup for inference and 1.6x throughput speedup for training.

Guo, Anqi↗
DOE OSTI2024

The Case for Co-Designing Model Architectures with Hardware

While GPUs are responsible for training the vast majority of state-of-the-art deep learning models, the implications of their architecture are often overlooked when designing new deep learning (DL) models. As a consequence, modifying a DL model to be more amenable to the target hardware can significantly improve the runtime performance of DL training and inference. In this paper, we provide a set of guidelines for users to maximize the runtime performance of their transformer models. These guidelines have been created by carefully considering the impact of various model hyperparameters controlling model shape on the efficiency of the underlying computation kernels executed on the GPU. We find the throughput of models with “efficient” model shapes is up to 39% higher while preserving accuracy compared to models with a similar number of parameters but with unoptimized shapes.

Yin, Junqi↗
DOE OSTI2019

Hardware-control v1

The software is a python module that makes it easy to create reusable interfaces to control common hardware used in experiments.

Persaud, Arun↗
DOE OSTI2022

ZHW hardware library

Hardware library implementation of the open source ZFP CODEC. ZHP provides a sub-set of the ZFP library compression and decompression functionality, but in the SystemC language rather than the C/C++ and Fortran languages used in the ZFP implementation.

Barrow, MichaelJ↗