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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 793 records · Page 44
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Power Module Precursors and Prognostics

This project focuses on finding and utilizing electrical properties (precursors) of power electronic devices and modules whose changes have strong correlations with different modes and levels of degradations in order to realize online and lightweight state of health evaluation and fault diagnosis. Results from this project will contribute to higher safety, reliability, and power density of power electronic components. The approaches mainly include reviewing academic literature and industry practices for state of the art precursor identification and extraction, accelerated life cycles (ALC) of various power modules to create different degradations in-house, and developing techniques for gate-driver-integratable precursor detection circuit. In FY24, the results includes two sets of definitively detected aging precursors (on-state resistance and gate threshold voltage) for two sets of power modules respectively, controlled accelerated lifetime cycling of multiple silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) modules, and the development and validation of a gate voltage detection system.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2025

Thermal Optimization and Experimental Demonstration of a Silicon Carbide, Half-Bridge Power Module

This paper describes modeling and experimental work to design and demonstrate a silicon carbide (SiC), single-side-cooled power module. Two SiC metal-oxide-semiconductor field-effect transistors (MOSFET) were used for each switch position and packaged on a metalized ceramic substrate. Thermal modeling was first conducted to optimize the module packaging to minimize junction-to-fluid thermal resistance and device temperature variations. This procedure identified the optimal device placement and baseplate thickness to maximize thermal performance. A heat exchanger - incorporating impinging jets of water-ethylene glycol - was designed to cool the module's baseplate to minimize thermal resistance and pumping power. The heat exchanger used relatively low fluid velocities (<1.5 m/s) to minimize erosion-corrosion effects and relatively large fluid channel sizes (>=1 mm) to prevent clogging. The power module concept was fabricated, and experiments were conducted to measure its thermal performance. Direct current was used to power the module devices, and junction temperatures were measured via device temperature-sensitive parameters. The experimental results were found to be in good agreement with model predictions (within 2%) and yielded junction-to-fluid thermal resistance values as low as about 15 mm2 K/W at relatively low pumping power values. The results demonstrate the improved performance associated with jet impingement cooling and represent an improvement over existing channel-flow-type cold plates, which can enable improvements to power density and reliability.

36 MATERIALS SCIENCE↗
NASA NTRS1984

Improved High-Current Drive Circuit

Uses VMOS field-effect power transistor. High-current drive circuit employs n-channel enhancement-mode VMOS field-effect power transistor to eliminate problem of oscillation at high power encountered in conventional circuits with bipolar transistors. Drive voltage required is typically 1 to 3 V for load current of 10 A.

Cole, S. W.↗
NASA NTRSDate not supplied

Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments

This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.

Silicon Carbide↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
DOE OSTI2022

Remote surface optical phonon scattering in ferroelectric Ba 0.6 Sr 0.4 TiO 3 gated graphene

We report the effect of remote surface optical (RSO) phonon scattering on carrier mobility in monolayer graphene gated by ferroelectric oxide. We fabricate monolayer graphene transistors back-gated by epitaxial (001) Ba 0.6 Sr 0.4 TiO 3 films, with field effect mobility up to 23 000 cm 2 V –1 s –1 achieved. Switching ferroelectric polarization induces nonvolatile modulation of resistance and quantum Hall effect in graphene at low temperatures. Ellipsometry spectroscopy studies reveal four pairs of optical phonon modes in Ba 0.6 Sr 0.4 TiO 3 , from which we extract RSO phonon frequencies. The temperature dependence of resistivity in graphene can be well accounted for by considering the scattering from the intrinsic longitudinal acoustic phonon and the RSO phonon, with the latter dominated by the mode at 35.8 meV. Furthermore, our study reveals the room temperature mobility limit of ferroelectric-gated graphene transistors imposed by RSO phonon scattering.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage ( V DS_SAT ) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance ( R ON ), and a higher V DS_SAT . Here, the challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in V DS_SAT is demonstrated, wherein it reduces from >12 to 5 V.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Toward AlGaN channel HEMTs on AlN: Polarization-induced 2DEGs in AlN/AlGaN/AlN heterostructures

Due to its high breakdown electric field, the ultra-wide bandgap semiconductor AlGaN has garnered much attention recently as a promising channel material for next-generation high electron mobility transistors (HEMTs). A comprehensive experimental study of the effects of Al composition x on the transport and structural properties is lacking. We report the charge control and transport properties of polarization-induced 2D electron gases (2DEGs) in strained AlGaN quantum well channels in molecular-beam-epitaxy-grown AlN/Al x Ga 1-x N/AlN double heterostructures by systematically varying the Al content from x = 0 (GaN) to x = 0.74, spanning energy bandgaps of the conducting HEMT channels from 3.49 to 4.9 eV measured by photoluminescence. This results in a tunable 2DEG density from 0 to 3.7 × 10 13 cm 2 . The room temperature mobilities of x ≥ 0.25 AlGaN channel HEMTs were limited by alloy disorder scattering to below 50 cm 2 /(V.s) for these 2DEG densities, leaving ample room for further heterostructure design improvements to boost mobilities. A characteristic alloy fluctuation energy of ≥1.8 eV for electron scattering in AlGaN alloy is estimated based on the temperature dependent electron transport experiments.

36 MATERIALS SCIENCE↗
NASA NTRS2005

Beyond G-band : a 235 GHz InP MMIC amplifier

We present results on an InP monolithic millimeter- wave integrated circuit (MMIC) amplifier having 10-dB gain at 235 GHz. We designed this circuit and fabricated the chip in Northrop Grumman Space Technology's (NGST) 0.07- m InP high electron mobility transistor (HEMT) process. Using a WR3 (220-325 GHz) waveguide vector network analyzer system interfaced to waveguide wafer probes, we measured this chip on-wafer for -parameters. To our knowledge, this is the first time a WR3 waveguide on-wafer measurement system has been used to measure gain in a MMIC amplifier above 230 GHz.

high electron mobility transistors (HEMTs)↗
DOE OSTI2024

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

Here we report a comparative study of three rectifying gate metals, W, Pd, and Pt/Au, on ultrawide bandgap Al 0.86 Ga 0.14 N barrier/Al 0.7 Ga 0.3 N channel high electron mobility transistors for use in extreme temperatures. The transistors were electrically characterized from 30 to 600 °C in air. Of the three gate metals, the Pt/Au stack exhibited the smallest change in threshold voltage (0.15 V, or 9% change between the 30 and 600 °C values, and a maximum change of 42%), the highest on/off current ratio (1.5 × 10 6 ) at 600 °C, and a modest forward gate leakage current (0.39 mA/mm for a 3,V gate bias) at 600 °C. These favorable results showcase AlGaN channel high electron mobility transistors' ability to operate in extreme temperature environments.

36 MATERIALS SCIENCE↗
DOE OSTI2022

High-density polarization-induced 2D electron gases in N-polar pseudomorphic undoped GaN/Al 0.85 Ga 0.15 N heterostructures on single-crystal AlN substrates

The polarization difference and band offset between Al(Ga)N and GaN induce two-dimensional (2D) free carriers in Al(Ga)N/GaN heterojunctions without any chemical doping. A high-density 2D electron gas (2DEG), analogous to the recently discovered 2D hole gas in a metal-polar structure, is predicted in a N-polar pseudomorphic GaN/Al(Ga)N heterostructure on unstrained AlN. We report the observation of such 2DEGs in N-polar undoped pseudomorphic GaN/AlGaN heterostructures on single-crystal AlN substrates by molecular beam epitaxy. With a high electron density of ~4.3 ×10 13 /cm 2 that maintains down to cryogenic temperatures and a room temperature electron mobility of ~450 cm 2 /V s, a sheet resistance as low as ~320 Ω/$\Box$ is achieved in a structure with an 8 nm GaN layer. Finally, these results indicate significant potential of AlN platform for future high-power RF electronics based on N-polar III-nitride high electron mobility transistors.

42 ENGINEERING↗
DOE OSTI2023

Scaling and statistics of bottom-up synthesized armchair graphene nanoribbon transistors

Bottom-up assembled nanomaterials and nanostructures allow for the studies of rich and unprecedented quantum-related and mesoscopic transport phenomena. However, it can be difficult to quantify the correlations between the geometrical or structural parameters obtained from advanced microscopy and measured electrical characteristics when they are made into macroscopic devices. Here, we propose a strategy to connect the nanomaterial morphologies and the device performance through a Monte Carlo device model and apply it to understand the scaling trends of bottom-up synthesized armchair graphene nanoribbon (GNR) transistors. A new nanofabrication process is developed for GNR transistors with channel length down to 7 nm. Further, the impacts of the GNR spatial distributions and the device geometries on the device performance are investigated systematically through comparison of experimental data with the model. Through this study, challenges and opportunities of transistor technologies based on bottom-up synthesized GNRs are pinpointed, paving the way to the further improvement of the GNR device performance for future transistor technology nodes.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Water-Surface Drag Coating: A New Route Toward High-Quality Conjugated Small-Molecule Thin Films with Enhanced Charge Transport Properties

Electronic properties of organic semiconductor (OSC) thin films are largely determined by their morphologies and crystallinities. However, solution-processed conjugated small-molecule OSC thin films usually exhibit abundant grain boundaries and impure grain orientations because of complex fluid dynamics during solution coating. Here, a novel methodology, water-surface drag coating, is demonstrated to fabricate high-quality OSC thin films with greatly enhanced charge transport properties. This method utilizes the water surface to alter the evaporation dynamics of solution to enlarge the grain size, and a unique drag-coating process to achieve the unidirectional growth of organic crystals. Furthermore, using 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (Dif-TES-ADT) as an example, thin films with millimeter-sized single-crystal domains and pure crystallographic orientations are achieved, revealing a significant enhancement (4.7 times) of carrier mobility. More importantly, the resulting film can be directly transferred onto any desired flexible substrates, and flexible transistors based on the Dif-TES-ADT thin films show a mobility as high as 16.1 cm 2 V -1 s -1 , which represents the highest mobility value for the flexible transistors reported thus far. The method is general for the growth of various high-quality OSC thin films, thus opening up opportunities for high-performance organic flexible electronics.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Role of Postdeposition Thermal Annealing on Intracrystallite and Intercrystallite Structuring and Charge Transport in Poly(3-hexylthiophene)

The performance of electronic devices comprising conjugated polymers as the active layer depends not only on the intrinsic characteristics of the materials but also on the details of the extrinsic processing conditions. Here, we examine the effect of postdeposition thermal treatments on the microstructure of poly(3-hexylthiophene) (P3HT) thin films and its impact on their electrical properties. Unsurprisingly, we find thermal annealing of P3HT thin films to generally increase their crystallinity and crystallite coherence length while retaining the same crystal structure. Despite such favorable structural improvements of the polymer active layers, however, thermal annealing at high temperatures can lead to a net reduction in the mobility of transistors, implicating structural changes in the intercrystallite amorphous regions of these semicrystalline active layers take place on annealing, and the simplistic picture that crystallinity governs charge transport is not always valid. Our results instead suggest tie-chain pullout, which occurs during crystal growth and perfection upon thermal annealing to govern charge transport, particularly in low-molecular-weight systems in which the tie-chain fraction is low. By demonstrating the interplay between intracrystallite and intercrystallite structuring in determining the macroscopic charge transport, we shed light on how structural evolution and charge-transport properties of nominally the same polymer can vary depending on the details of processing.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Au-free low-temperature ohmic contacts for AlGaN/AlN/GaN heterostructures

We report Au-free, Ti/Al/Ta ohmic contact on the AlGaN/AlN/GaN heterostructure using low annealing temperature is studied in this paper. With SiCl 4 plasma treatment at the recess-etched contact region, a low contact resistance of 0.52 Ω mm and a low sheet resistance of 373 Ω/sq are achieved after annealing at 550 °C for 30 s. The low annealing temperature also leads to better surface morphology. Furthermore, AlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) are fabricated with the 550 °C, 30 s annealed Ti/Al/Ta ohmic contacts, and a maximum transconductance of 123 mS/mm and a maximum drain current of 510 mA/mm are obtained for a gate length of 4 μm. Based on Silvaco's Atlas device simulation framework, a scaled-down device with a short gate length of 1 μm would produce a maximum drain current density of 815 mA/mm. It indicates that the direct current performance of the HEMTs with the ohmic metal proposed in this work is considerably better than that with Au-based ohmic contact.

42 ENGINEERING↗